Analog Layout Engineer

Analog Layout Engineer We are seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization. In this role, you will contribute to cutting‑edge analog and mixed‑signal IP development, working across complex technologies such as FinFET and deep sub‑micron processes. This is an excellent opportunity for a hands‑on layout expert who thrives in technically challenging environments and enjoys end‑to‑end ownership from block‑level design through top‑level integration. Responsibilities Independently develop block‑level and IP‑level analog/RF layouts , partnering closely with circuit designers and global layout teams to drive designs from concept to tape‑out. Own floorplanning, placement, routing, and optimization for complex analog and mixed‑signal blocks, including SerDes, ADC/DACs, PLLs, and related IPs . Lead and support top‑level integration of multiple analog and mixed‑signal blocks within larger SoCs. Apply deep expertise in advanced deep sub‑micron and FinFET process technologies , incorporating fabrication, EM, ESD, latch‑up, and reliability considerations into layouts. Resolve complex DRC, LVS, antenna, and verification issues , exercising strong technical judgment while collaborating across geographies and mentoring or guiding team members as a technical lead. Qualifications Bachelor’s degree in Electrical Engineering, Electronics, or a related field. 6+ years of hands‑on experience in analog and/or RF layout design (8+ years preferred). Proven experience with analog floor planning and layout for complex modules such as SerDes, ADC/DAC, PLLs, and similar high‑speed or precision circuits . Strong understanding of analog layout best practices for deep sub‑micron CMOS and FinFET technologies . Compensation The base compensation range for this role in the posted location is: $97,700 to $203,800 per year. Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction. Benefits Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12‑25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave Medical, dental, and vision coverage (or provincial healthcare coordination in Canada) Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada) Life and disability insurance Employee assistance programs Other benefits as provided by local policy and eligibility Location San Francisco, CA; Santa Clara, CA, US Equal Opportunity Employer Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law. #J-18808-Ljbffr Capgemini