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Senior Analog Layout Engineer

$86.9k - $203.8k

Capgemini

Senior Analog Layout Engineer - San Jose CA At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life‑saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same. About the Role Senior layout designer, will be responsible for layout of high‑performance analog cores such as analog‑to‑digital converters, digital‑to‑analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting‑edge high‑performance, high‑speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry. Key Responsibilities Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys. Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools. Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc. Experience with floor planning, block‑level routing, and top‑level chip assembly. Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration. Demonstrated experience with analog layout for silicon chips in mass production. Experience working with distributed design teams. Knowledge of SKILL code and layout automation. Self‑starter with the ability to define and adhere to a schedule. Strong written and verbal communication skills. Your Profile 10+ years of experience in high‑performance analog layout in advanced CMOS process. Experience With FinFET Process Nodes (preferred) Compensation The base compensation range for this role in the posted location is $86,900 - $203,800 / year. Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction. These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity. It is not typical for candidates to be hired at or near the top of the posted compensation range. In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws. Benefits Capgemini offers a comprehensive, non‑negotiable benefits package to all regular, full‑time employees. In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include: Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12‑25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave Medical, dental, and vision coverage (or provincial healthcare coordination in Canada) Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada) Life and disability insurance Employee assistance programs Other benefits as provided by local policy and eligibility Important Notice Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation. Disclaimers Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law. This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact. Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process. #J-18808-Ljbffr Capgemini

Vacancy posted 1 day ago
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