ASIC Power Engineer, ML Accelerators

corporate_fare Google place Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.). Experience with RTL (Register Transfer Level) design using Verilog or SystemVerilog. Preferred Qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience interacting with software, architecture, and other cross‑functional teams. Experience with a scripting language (e.g., Python or Perl). Experience applying engineering best practices (e.g., code review, testing, refactoring). Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms. Knowledge of high performance and low power design techniques. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi‑faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. Contribute to design power modeling and drive convergence to power goals. Investigate, specify, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low‑power designs. Collaborate with cross‑functional software and system teams to create novel power management architectures to meet power goals. Individual pay is determined by factors including job‑related skills, experience, and relevant education or training. US: $163,000 - $237,000 (USD) + 15% bonus target + equity + benefits. Learn more about benefits at Google. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. #J-18808-Ljbffr Google