Senior IC Packaging Engineer

Job Description

Job Description

Integrated circuit Packaging Engineer

Location: Senior IC Packaging Engineer
Job Type: Full-Time
Work Arrangement: On-site

Job Overview

We are seeking a Senior IC Packaging Engineer to lead the architecture, design, development, and optimization of advanced semiconductor packaging technologies for next-generation high-performance computing and optical interconnect applications.

The ideal candidate will have strong hands-on experience in advanced IC packaging, wafer-level processes, TSV reveal, C4 bumping, 2.5D/3D packaging, and OSAT manufacturing , along with a strong background in process development, yield improvement, and NPI-to-HVM transfer.

Key Responsibilities

• Lead development of advanced packaging solutions including 2.5D/3D IC, SiP, Flip-Chip, and Wafer-Level Packaging .
• Develop and optimize TSV reveal processes , including back grinding, CMP, dielectric/barrier reveal etch, and wafer thickness/uniformity control.
• Own C4 bumping processes , including UBM deposition, solder bump plating or ball attach, reflow, and flux cleaning.
• Develop SPC, DOE, process control plans, and yield improvement strategies .
• Work with integration engineering teams to optimize TSV reveal with hybrid bonding, micro-bump, and RDL processes .
• Troubleshoot process excursions using failure analysis, cross-sections, and metrology data.
• Investigate defects such as TSV protrusion, via reveal non-uniformity, bump voiding, and co-planarity issues.
• Support NPI from technology development through HVM transfer .
• Collaborate with design, reliability, test, equipment, and manufacturing teams.
• Mentor junior engineers and contribute to process documentation and best practices.

Required Qualifications

• MS or PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering , or a related field.
• 5+ years of hands-on semiconductor packaging or wafer fab process engineering experience .
• Experience working with major OSATs such as ASE, Amkor, or SPIL.
• Direct experience with TSV reveal , including grinding, CMP, dielectric reveal, and thickness metrology.
• Hands-on experience with C4 bumping , UBM, electroplating or solder ball attach, and reflow.
• Strong understanding of 2.5D/3D IC packaging , interposers, chiplets, and HBM integration.
• Knowledge of semiconductor device physics, packaging materials, and thermal/mechanical analysis.
• Experience with SPC, DOE, yield analysis, and process optimization .
• Familiarity with packaging metrology and inspection tools such as:
• • CD-SEM
  • AFM
  • Profilometry
  • X-ray
  • AOI/SEM defect review
• Working knowledge of cleanroom operations and contamination control.
• Strong communication and cross-functional collaboration skills.

Preferred Qualifications

• Experience with copper pillar, micro-bump, or hybrid bonding .
• Experience with wafer thinning and temporary bonding/debonding.
• Exposure to package reliability testing such as thermal cycling, electromigration, and HAST .
• Experience supporting HVM ramp in an OSAT or IDM environment.