Senior FPGA DDR & IO Subsystem Architect

191 Altera Corporation is looking for a leading architect in High-Speed External Memory systems to develop innovative solutions. The role requires extensive experience in RTL design, memory technologies, and cross-functional collaboration. The ideal candidate will possess a minimum of a Bachelor's Degree in Electrical Engineering and 10+ years of relevant experience. This position is based in San Jose, California and offers a competitive salary range of $200,400 – $286,000, along with performance-based incentives. #J-18808-Ljbffr 191 Altera Corporation