Senior FPGA DDR & IO Subsystem Architect
$200.4k - $286kAltera
A leading innovator in FPGA technology is seeking an FPGA DDR and IO Subsystem Architect in San Jose, California. In this technical leadership role, you will define architecture for high-speed external memory and general-purpose IO subsystems. The ideal candidate will have over 10 years of experience in RTL design and expertise in DDR technologies. This opportunity offers a competitive salary range of $200,400 - $286,000 USD. #J-18808-Ljbffr Altera
Vacancy posted 3 days ago
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