Senior FPGA Debug & Verification Architect
$149.1k - $215kAltera
Altera is seeking a Senior Debug Verification Engineer in San Jose, California to oversee design verification tasks including creating test cases and employing UVM methodology. The ideal candidate will have over 8 years of experience in ASIC designs, SystemVerilog, and UVM verification methodologies. Key responsibilities include pre-silicon system verification, creating test cases, and coordinating with cross-functional teams. The salary range for this position is $149,100 - $215,000 per year. #J-18808-Ljbffr Altera
Vacancy posted 3 days ago
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