Lead PLL Design Architect for High-Speed Transceivers
Jobleads-US
Celero Communications, Inc. is seeking a Principal PLL Design Engineer to lead the clocking subsystem for next-generation high-speed interconnects.
You will architect and implement PLLs for transceivers, collaborating with mixed-signal teams to achieve stringent jitter and phase-noise targets. The role requires a Master’s or PhD in Electrical Engineering with 5+ years of PLL design and hands-on experience across 16nm–2nm nodes, VCO design, and tape-out readiness.
#J-18808-Ljbffr Jobleads-USVacancy posted 7 hours ago
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