SoC Principal Physical Design Engineer

Please note: Preferred location is Auston, however alternate locations can be Dallas, Phoenix and Mountain View.

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent over a decade taking complex SoCs from RTL to silicon, and you know that the difference between a chip that meets PPA and one that doesn't often comes down to decisions made during floorplanning or a CTS strategy that accounts for what the foundry PDK will actually give you at 3nm. You are the engineer who sees congestion coming three steps ahead and adjusts before it becomes a crisis that delays tapeout.

Working at advanced nodes is not new to you. You have closed timing on multi-billion transistor designs where every picosecond matters and every milliwatt counts. You know when to push the tools harder and when to step back and rethink the approach. Customers trust you because you do not just run flows, you understand why they work and when they won't.

You are comfortable leading technical conversations with design teams, applications engineers, and customers who need real answers, not platitudes. Mentoring comes naturally because you remember what it was like to debug your first IR drop violation at 2am before tapeout. At Synopsys, you will work on the hardest physical design problems in the industry, with the tools that define the state of the art, and with customers who are building the next generation of silicon.

What You'll Be Doing

• Lead full-chip and block-level physical implementation from RTL through GDSII tapeout on advanced-node designs at 5nm, 3nm, and below
• Define and execute floorplanning, power planning, placement, clock tree synthesis, routing, and signoff strategies that hit PPA targets
• Drive timing closure, power optimization, congestion reduction, and area improvement using Fusion Compiler, PrimeTime, and StarRC
• Perform and review static timing analysis, ECO implementation, IR-drop analysis, electromigration checks, and physical verification using IC Validator
• Work directly with semiconductor customers to enable their success, troubleshoot design challenges, and deliver technical workshops and methodology guidance
• Develop automation scripts and flows using Python, Tcl, and shell scripting to improve design productivity and methodology efficiency
• Leverage AI and ML-based physical design technologies including DSO.ai and Fusion Compiler optimizations to accelerate closure and explore the design space

The Impact You Will Have

• Enable customer tapeouts on the most advanced process nodes in the industry, directly influencing the success of next-generation AI, mobile, and high-performance computing chips
• Establish physical design methodologies and best practices that scale across large SoC programs and improve turnaround time for multi-billion transistor designs
• Translate real-world design challenges into actionable requirements that shape the roadmap for Synopsys implementation and signoff tools
• Mentor and elevate junior engineers, building technical depth across the team and raising the bar for design closure strategies
• Deliver designs that meet aggressive PPA targets and tapeout schedules, proving out methodologies that customers will adopt across their portfolios
• Drive automation and flow innovation that reduces manual effort, catches issues earlier, and makes complex physical design more predictable
• Influence foundry engagement and tool development by surfacing what works and what breaks at the cutting edge of semiconductor technology

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 10 to 15+ years of hands-on ASIC or SoC physical design experience with a proven track record of multiple successful tapeouts at advanced process nodes
• Deep expertise in floorplanning, power planning, place and route, clock tree synthesis, timing closure, and physical verification including DRC and LVS
• Strong working knowledge of IR-drop analysis, electromigration analysis, and ECO methodologies for late-stage design fixes
• Proficiency in scripting languages including Python, Tcl, Perl, or shell for automation and flow development
• Experience with Synopsys tools such as Fusion Compiler, PrimeTime, IC Validator, StarRC, Formality, and PrimePower is a strong plus
• Familiarity with foundry technologies from TSMC, Samsung, or Intel and an understanding of what changes at 5nm and below is highly valued

Who You Are

• You can walk into a customer meeting, listen to a design problem, and sketch out a viable closure strategy on a whiteboard without needing to run back to the lab first
• When a design is failing setup by 200ps two weeks before tapeout, you do not panic, you methodically work the problem, prioritize the right fixes, and communicate progress clearly to stakeholders
• You have a point of view on methodology and you are not afraid to push back when a flow does not make sense or a customer request will create more problems than it solves
• Mentoring is something you do because you care, not because it is on a performance review, and junior engineers leave conversations with you with a clearer picture of what to do next
• You are organized enough to juggle multiple tapeout schedules, customer engagements, and internal projects without dropping threads or losing track of what matters most
• You write automation that other engineers actually use because it solves a real problem and does not require a PhD to understand

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.