TPU PCIe RTL Design Lead — AI Accelerator
Google Sunnyvale seeks a PCIe Design Engineer to shape the PCIe/SoC RTL for next-generation data center accelerators. You will architect and implement SoC-level RTL, building core infrastructure like clocking, reset, and chip management, while collaborating with software and hardware teams to deliver high-performance accelerators. You will contribute to TPUs and AI hardware efforts, verifying complex digital designs with emphasis on TPU architecture integration within AI/ML systems. #J-18808-Ljbffr Google
Vacancy posted 2 days ago
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