TPU ASIC Physical Design Lead - High-Impact AI Silicon
Google LLC
Google LLC in Sunnyvale, CA is seeking a skilled hardware design engineer to drive the physical design of high-performance ASIC sub-chips for TPU architectures, from RTL to GDSII, with focus on timing, power, and area. Join the AI and Infrastructure team to shape cutting-edge TPU hardware, collaborate with RTL, DFT, packaging teams, and partners, and contribute to Google's scalable AI platforms. #J-18808-Ljbffr Google LLC
- ...for a leadership role in AI/ML hardware acceleration, focusing on TPU architecture and its... ...systems. You will drive the physical design of critical sub-chips... ...the next-generation AI silicon, leading cross-functional teams... ...to ensure scalable, high-performance designs. The...Suggested
$192k - $278k
...of experience in physical design, including leading full-chip or sub... ...closure for high-speed ASICs across various process... ...the future of AI/ML hardware... ...drive cutting-edge TPU (Tensor Processing... ...custom silicon solutions that power... ...agreement. They have no impact on statutory...SuggestedWorldwide$192k - $278k
Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity... ...closure for high-speed ASICs across various process nodes.... ...design of our next-generation AI silicon. Because of the sheer...SuggestedWorldwide$192k - $278k
Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.Manage... ...for high-speed ASICs across various process... ...shape the future of AI/ML hardware acceleration... ...to drive cutting-edge TPU (Tensor Processing...SuggestedWorldwide$240k - $333k
Design, build, and scale constrained-... ...SystemVerilog and UVM for high-speed physical-layer DSP... ...profiles.Lead the debugging of... ...and roadmaps for AI accelerators,... ...bandwidth networking silicon.Experience... ...cutting-edge TPU (Tensor Processing... ...systems. As an ASIC Design...SuggestedWorldwideShift work$192k - $278k
...closure, and physical signoff.Understand... ...optimal design closure.Develop... ...signoff.Lead sub-chip execution... ...(ALUs) into high-frequency,... ...and metal-fill impacts on dense structures... ...future of AI/ML hardware... ...cutting-edge TPU (Tensor... ...developing custom silicon solutions that...Worldwide- Google is seeking a senior hardware design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, verify complex digital designs, and... ...place and route (PNR), timing closure, and physical signoff. You will mentor a small team and collaborate...
$194.6k - $285.7k
...the TeamCisco Silicon One (#CiscoSiliconOne... ...complex and high-performance Silicon ASICs. Our silicon... ...IC package design and heterogeneous... ...Technical Lead Hardware Board... ...will lead high-impact, cross-functional... ...in the AI era - and beyond... ...together across the physical and digital...Full timeContract workTemporary workWork at officeLocal areaFlexible hoursShift work$192k - $278k
Share TPU Design Verification Engineering Lead corporate_fare Google place... ...an SoC or large ASICs. Experience in... ...functional teams for high quality tape‑... ...bug‑free Silicon in complex SoCs.... ...best of Google AI, Software, and Hardware... ...agreement. They have no impact on statutory...Worldwide$230k
Principal ASIC Engineering Lead (Physical Design OR STA)Up to $230k base, + 30% bonus plus around $800k... ...passion for working on bleeding-edge AI and high-performance silicon? Have you delivered enough chips... ...in EDA reports before they impact schedules, and can you clearly explain...- ...In this highly visible hands-on role you will lead a team of engineers at... ...Apples SOC IP DMA design effort. Balancing... ...will ensure silicon-ready quality while... ...will have direct impact on products used... ...As a hands-on ASIC Design Engineering... ...use of AI and other emerging...Full timeWorldwide
$192k - $278k
Lead the PCIe microarchitecture and... ...development, ensuring high-performance designs that strictly... ...and Physical Design teams to... ...and lead post-silicon bring-up to ensure... ...experience in ASIC design, including... ...the future of AI/ML hardware acceleration... ...cutting-edge TPU (Tensor...Worldwide$186.9k - $267.7k
...the TeamCisco Silicon One (#CiscoSiliconOne... ...complex and high-performance Silicon ASICs. Our silicon... ...IC package design and heterogeneous... ...Technical Lead to help us develop... ...Review & Physical Validation: Experience... ...in the AI era - and beyond... ..., our impact is everywhere....Full timeTemporary workLocal areaRemote workFlexible hours$186.9k - $267.7k
...platforms central to the AI era, powering Cisco... ...Our innovations in silicon, optics, and... ...product development—from design to qualification to... ....Work closely with physical design team to... ...engineering and 8+ years of ASIC Design experience,... ...everywhere, our impact is everywhere. We...Full timeTemporary workLocal areaFlexible hours$192k - $278k
Lead the functional verification team... ...significant portions of TPU Compute team,... ...-functional design, architecture... ...functional efforts for silicon bring-up.Partner... ...verification of high-performance... ...subsystems for AI/ML accelerators.... ...systems. As an ASIC Design Verification...Worldwide- ...in Sunnyvale, CA is seeking a senior hardware designer to shape the future of AI/ML hardware acceleration. You’ll own critical datapath... .... The role requires a track record in physical design, sub-7nm processes and high-density macros, plus leadership of a small team...
- Google Sunnyvale seeks a PCIe Design Engineer to shape the PCIe/SoC RTL... ...software and hardware teams to deliver high-performance accelerators. You will contribute to TPUs and AI hardware efforts, verifying... ...designs with emphasis on TPU architecture integration within...
$250k - $280k
...Eridu Eridu is a Silicon Valley-based... ...that accelerate AI data centers to... ...widely validated by leading hyperscalers.... ...a hands-on ASIC Chip Design Lead to own chip... ...verification, and physical design teams. This is a highly technical, roll... ...will directly impact the next...Full time$171.6k - $245k
...central to the AI era, powering... ...in silicon, optics, and... ...development—from design to qualification... ...most complex ASICs being developed... ...new class of high-performance routers... ...ImpactAs a Lead Hardware... ...together across the physical and digital... ..., our impact is everywhere...Full timeContract workTemporary workWork at officeLocal areaFlexible hours- ...generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling... ...forward.THE ROLE: We are seeking a lead Physical Design Engineer to ensure that... ...meet Thermal requirements and Silicon Performance. This is a...
$171.6k - $245k
...central to the AI era, powering... ...in silicon, optics, and... ...development—from design to qualification... ...world. Your Impact Hardware design technical lead is a key member... .../or merchant ASIC.Responsible for... ...with complex high-speed board... ...together across the physical and digital...Full timeTemporary workLocal areaFlexible hours$192k - $278k
Lead, mentor, and manage a team of RTL Design Engineers performing tasks... ...Design for Test, Physical Design, and... ...Chip Design, ASIC Digital... ...Knowledge of high performance and... ...the future of AI/ML hardware acceleration... ...cutting-edge TPU (Tensor... ...custom silicon solutions that...Worldwide$220k - $250k
...looking for a seasoned RTL Design Tech Lead to drive micro-... ...execution for complex ASIC/SoC programs. This role... ...mindset, has led successful silicon bring-ups, and can... ...closely with: Physical Design (PD) STA / Timing... ...Timing / DFT teams Ensure high RTL quality via: Low-...$220.92k - $311.89k
...Description: The Role and Impact As a Physical Design Timing Engineer, you... ...'s ability to deliver high-performance, power-... ...knowledge of industry-leading EDA tools. Join us in... ...methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement...Full timeLocal areaImmediate startShift work$220.92k - $311.89k
...are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional... ...ensure first-pass silicon success. As a... ...with AI/ML accelerators... ...make a lasting impact on Intel's groundbreaking... ...), Custom ASIC (leveraging... ...ancestry, age, physical or mental...Full timeWork experience placementLocal areaImmediate startWorldwideShift workNight shift$192k - $278k
...verification team for portions of TPU designs, setting and... ...to shape the future of AI/ML hardware acceleration... ..., developing custom silicon solutions that power the... ...-driven systems. As an ASIC Design Verification Manager... ...TPU designs, you will lead a team and own the...Worldwide$167k - $275k
...GlobalFoundries is a leading full-service... ...unique combination of design, development, and fabrication... ..., and successful silicon execution. The... ..., verification, physical design, DFT, firmware... ...implementation for high-performance and low... ...multicore processors, AI accelerators, or...Full timeLocal area- ...discovery to powering AI and the... ...Whether you’re designing next-gen processors... ..., or bringing leading edge products... ...a Director of Silicon Architecture to... ...while leading high-performing teams... ...EXPERIENCEExperience in FPGA, ASIC, or SoC... ..., mental or physical disability,...
- ...in Sunnyvale is seeking an experienced ASIC Design Engineering Lead to head a team central to the SoC IP... ...architecture, RTL delivery, and debug to ensure silicon-ready quality. You will guide... ...mentor engineers, and drive automation and AI-enabled tooling while coordinating...
- Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a CPU Physical Design Integration engineer, you will lead end-to-end integration, physical verification and final tape-out signoff checks, collaborating with packaging...
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