Senior RTL Design Lead for AI Connectivity Chips
Astera Labs
Astera Labs in San Jose, CA, is hiring a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI clusters. You will own RTL design from microarchitecture through synthesis sign-off, delivering high-quality Verilog/SystemVerilog blocks. Collaborate with architecture, verification, DFT, and physical design to move features from spec to silicon, mentor engineers, drive timing closure, and ensure scalable design methodologies for aggressive tapeouts. #J-18808-Ljbffr Astera Labs
Vacancy posted 2 days ago
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