Senior/Staff Analog IC Design Engineer

About PowerLattice PowerLattice is a well‑funded semiconductor startup backed by leading Silicon Valley venture capital firms. We are developing a groundbreaking chiplet solution for a fundamental shift in how high‑performance chips are powered, paving the way for the next generation of AI and advanced computing. The Role We are seeking a motivated and detail‑oriented Senior or Staff level Analog IC Designer to join our engineering team. In this role, you will design and develop high‑quality analog and mixed‑signal integrated circuits, contributing to fundamental analog building blocks from initial specification through post‑layout verification and silicon validation. You will work closely with cross‑functional teams, including layout, verification, and silicon validation, and play a key role in delivering robust, production‑ready designs. Key Responsibilities Design and develop core analog and mixed‑signal circuit blocks, including bandgap references, oscillators, LDOs, op‑amps, ADCs, and DACs Translate system and block‑level specifications into robust circuit architectures and implementations Perform schematic capture, simulation, and optimization to meet performance, power, area, and reliability targets Provide layout guidance and collaborate closely with layout engineers to ensure design intent is met Perform post‑layout (PEX) simulations and correlations with pre‑layout analysis Participate in design reviews and contribute to clear, thorough design documentation Support silicon bring‑up, block‑level evaluation, characterization, and debugging Apply best practices for analog design, verification, and sign‑off Minimum Qualifications This role is Hybrid requiring 3 days a week onsite in the office. Bachelor’s degree in Electrical Engineering, Computer Science or a related field 5+ years of hands‑on analog design experience Strong foundation in analog circuit theory, device physics, and CMOS technologies Experience designing common analog blocks such as bandgaps, LDOs, oscillators, op‑amps, ADCs, and DACs Proven ability to carry designs from specification through schematic, simulation, layout guidance, and post‑layout verification Proficiency with industry‑standard EDA tools (e.g., Cadence) Solid experience with DC, AC, transient, noise, and corner simulations Working knowledge of reliability, mismatch, and layout‑dependent effects Hands‑on laboratory experience, including silicon bring‑up, bench characterization, and debugging of analog/mixed‑signal ICs Preferred Qualifications Experience with deep submicron CMOS process technologies Familiarity with high‑power or high‑accuracy analog design techniques Strong communication skills and the ability to work effectively in a collaborative team environment Compensation & Benefits Anticipated annual base salary for Member of Technical Staff: $150,000 - $200,000. Stock option grant Comprehensive benefits package including health, dental, vision, and 401(k) #J-18808-Ljbffr Powerlattice Technologies Inc