Senior Emulation Architect, RISC-V Systems
$105k - $260kVentana Micro Systems
Ventana is building the highest-performance RISC-V CPUs on the planet—designed for data center, AI, and edge workloads, with real silicon, not slideware. Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64‑bit ARM server processor (X‑Gene at AppliedMicro)—bringing decades of CPU innovation to a clean‑slate, open‑standards future. Ventana is looking to fill multiple technical Senior Engineer positions to continue the development of its innovative RISC‑V processors and subsystems. We seek experienced professionals who can successfully work cross‑functionally between all pre‑silicon disciplines (arch/uarch, design, DV, software, performance, emulation/prototyping), with the focus on the development, debugging, and maintenance of complex system‑level hybrid execution environments to enable pre‑silicon bring‑up of system software and performance benchmarking workloads. Requirements 8+ years industry experience Bachelor’s or Master’s or PhD degree in a related engineering field Ability to take initiative, work independently and across geographies Strong domain knowledge of computer architecture Preferred Skills & Qualifications Hands‑on experience with commercial emulation (Cadence Palladium, Mentor Veloce) and/or prototyping (Cadence Protium, HAPS) solutions: transactor development, virtual prototyping, implementation/enablement of flows for advanced verification techniques (assertions, coverage, UPF) Good understanding of modern SystemVerilog for design and verification Strong software development experience in compiled (C/C++) and interpreted (Python, Tcl) languages Strong hardware/software co‑debug skills Exposure to isolating and reproducing silicon bugs in emulation Hands‑on knowledge of firmware, OS (Linux, RTOS) and hypervisor (Xen, KVM) open source software stacks for embedded and server applications Industry experience with CPU architectures (RISC‑V, x86, armv8), coherent communication protocols and standard IO interfaces Crisp and clear communication skills Base Salary Range $105,000 TO $260,000 per year EEO Statement Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law. COVID‑19 Vaccination Requirement Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID‑19. We do require proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/business partners. #J-18808-Ljbffr Ventana Micro Systems
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...infrastructure, and collaborating with software teams. Candidates should have a degree in engineering and an in-depth understanding of RISC-V ISA. The offered base salary ranges from $105,000 to $260,000 per year, depending on experience. #J-18808-Ljbffr Ventana Micro SystemsSuggested$105k - $260k
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