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Remote RTL Design Engineer for AI-Driven ASICs

$100 - $175 per hour

Mercor

Mercor in San Francisco is looking for RTL Design Engineers to enhance AI model training for chip design. The role requires experience in digital RTL design and strong skills in Verilog/SystemVerilog. You'll work on design, implementation, and collaboration with other teams, utilizing EDA tools. This is a contract position, remote for 40 hours/week, with compensation ranging from $100 to $175/hour. Applications are reviewed on a rolling basis, starting in the week of 04/23. #J-18808-Ljbffr Mercor

Vacancy posted 20 hours ago
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