Design for Test Engineer - RISC-V - Contractor

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking a highly skilled Design for Test (DFT) Engineer for a 6-month+ contract to contribute to high-performance designs within cutting-edge AI/ML architectures. In this role, you will be involved in all aspects of DFT implementation from RTL to tapeout for various IPs on the chip. You will work closely with experienced engineers across multiple domains of ASIC design to optimize test cost, maximize coverage, and facilitate efficient debug and yield learning while minimizing design intrusions.

This role is   hybrid or remote, based out of Austin, TX or Santa Clara, CA.

Responsibilities:

• Implement DFT features into RTL using Verilog.


• Develop and optimize DFT architectures and micro-architectures.


• Perform ATPG and test coverage analysis using industry-standard tools.


• Implement JTAG, Scan Compression, and ASST techniques.


• Conduct gate-level simulation using Synopsys VCS and Verdi.


• Support silicon bring-up and debug activities.


• Plan, implement, and verify MBIST.


• Collaborate with Test Engineering for test planning, pattern generation, and debug.


• Develop efficient DFx flows and methodologies compatible with front-end and physical design processes.

Experience & Qualifications:

• BS/MS/PhD in EE, ECE, CE, or CS with 5+ years of industry experience in advanced DFx techniques.


• Hands-on experience implementing DFx in finFET technologies.


• Proficiency in industry-standard ATPG and DFx insertion CAD tools.


• Familiarity with SystemVerilog and UVM.


• Strong RTL coding skills for DFx logic, including lock-up latches, clock gates, and scan anchors.


• Understanding of low-power design techniques such as power gating, multi-Vt, and voltage scaling.


• Solid knowledge of high-performance, low-power design fundamentals.


• Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.


• Exposure to post-silicon testing and tester pattern debug (a major plus).


• Experience with Fault Campaigns is a plus.


• Strong problem-solving and debugging skills across multiple levels of design hierarchy.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.