Technical Architect - SoC, Verilog, UVM, C, C++

Technical Architect - SoC, Verilog, UVM, C, C++ Job Summary We are seeking highly motivated Design Verification Engineers to verify a next-generation UALink Controller IP used in AI and HPC platforms. The engineer will develop scalable verification environments capable of achieving functional, protocol, and performance closure for one of the industry's highest‑bandwidth interconnect controllers. The role requires expertise in constrained‑random verification, protocol checking, coverage‑driven verification, and debugging complex hardware interactions. Key Responsibilities Develop UVM‑based verification environments. Build functional coverage models. Write assertions (SVA). Develop protocol monitors and checkers. Create directed, random, and stress tests. Perform regression analysis. Debug RTL issues using waveform analysis and transaction logs. Collaborate closely with RTL designers. Skill Requirements Strong communication and cross‑functional collaboration with architecture, design teams. Excellent debugging and problem‑solving skills. Compensation and Benefits A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance‑based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need‑based leave with no designated number of leave days per year); and 10 paid holidays per year. #J-18808-Ljbffr HCL Technologies Limited