Physical Design Implementation and STA Lead

About Altera At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry. About the Role We are seeking an experienced Physical Design Implementation & Static Timing Analysis (STA) Lead to play a key technical role in delivering high‑quality physical implementation and timing closure for next‑generation FPGA SoCs. In this role, you will lead physical design implementation and static timing analysis activities for complex blocks and SoC subsystems, driving implementation from floorplanning through final timing closure while partnering closely with RTL, architecture, DFT, CAD, and signoff teams. This is a highly technical individual contributor role with project leadership responsibilities. You will provide technical guidance to engineers across implementation and timing closure activities while helping improve methodologies and evaluating emerging ML/AI‑assisted physical design technologies. Key Responsibilities Lead block‑level physical implementation including synthesis, floorplanning, place‑and‑route, clock tree synthesis (CTS), optimization, and ECO closure. Support SoC‑level physical implementation and collaborate on floorplanning, partitioning, and integration strategies. Develop and maintain implementation constraints (SDC and UPF) to meet timing, power, and area (PPA) goals. Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle. Drive implementation convergence across timing, power, congestion, and routability objectives. Contribute to methodology improvements and implementation best practices. Perform static timing analysis (STA) using Synopsys PrimeTime or equivalent STA tools; identify and resolve setup, hold, recovery, removal, SI/crosstalk, and clock‑related timing violations. Drive timing‑driven ECO implementation in collaboration with RTL and physical design teams. Develop timing constraints and validate timing exceptions to ensure robust signoff quality. Partner with library, CAD, and methodology teams to improve timing closure efficiency. Execute signoff activities including IR drop, electromigration (EM), DRC, LVS, antenna, and physical verification. Analyze congestion, routing quality, clock quality, and PPA tradeoffs. Support implementation planning to achieve project schedules and tapeout milestones. Utilize ML/AI‑assisted implementation technologies, develop Tcl and Python automation to streamline workflows, collaborate with CAD teams on AI‑assisted optimization methodologies, and analyze implementation metrics to identify optimization opportunities. Provide technical leadership for physical implementation and STA activities across multiple projects; mentor junior and mid‑level engineers, participate in design and timing reviews, contribute to reusable methodologies, automation, and engineering best practices. Qualifications Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline with 7+ years of industry experience in physical design, implementation, or static timing analysis. 7+ years of experience in physical design, implementation, or SoC backend development for advanced semiconductor products. 5+ years of experience performing block‑level physical implementation (synthesis, floorplanning, place‑and‑route, CTS, optimization, and ECO closure). 3+ years of experience performing static timing analysis using Synopsys PrimeTime or equivalent STA tools, including multi‑mode multi‑corner (MMMC) timing analysis. Preferred Qualifications: Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. 10+ years of experience in physical design and static timing analysis for advanced semiconductor products. Experience with advanced process technologies including 7nm, 5nm, or below. Experience with SoC physical implementation and top‑level timing closure. Experience with high‑speed interface implementation including PCIe, Ethernet, SerDes, DDR, LPDDR, HBM, or similar technologies. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including location, job‑related knowledge, skills, experiences, trainings, etc. Incentive opportunities are also available.

$149,100 – $215,000 USD.

Job Type Regular. Shift: Shift1 (United States of America). Primary Location: SanJose, California, UnitedStates. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Additional Information We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. #J-18808-Ljbffr 191 Altera Corporation