DV Engineer

Job Description

Job Description

Senior ASIC/SoC Design Verification Engineer (Chip-Level Verification)

An outstanding, full-time opening is available in Silicon Valley, CA for an experienced ASIC/SoC Design Verification Engineer with deep expertise in chip-level verification of complex SoCs and multi-IP integrated systems .

This role requires proven experience owning end-to-end pre-silicon verification from planning through coverage closure and tapeout readiness in a high-performance engineering environment. This is a fully onsite role (5 days/week) in the South Bay Area. Compensation up to $225K DOE + strong benefits + long-term project stability

All candidates MUST have the following experiences to qualify for consideration:

• 8+ years of ASIC/SoC Design Verification experience with significant chip-level verification exposure
• Extensive chip-level / full SoC verification ownership , including planning, execution, and closure of verification for complex multi-IP SoCs
• Strong hands-on experience developing and maintaining SystemVerilog/UVM-based verification environments , including drivers, monitors, scoreboards, sequences, agents, and coverage models
• Experience defining and executing verification plans (vPlan) and coverage-driven verification strategies
• Strong expertise in functional, code, assertion (SVA), and toggle coverage closure
• Hands-on experience with debugging RTL and verification environments , including root-cause failure analysis
• Experience with regression planning, execution, and failure triage at chip-level scale
• Strong experience with AMBA protocols (AXI, AHB, APB) and multi-IP subsystem integration
• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa
• Experience developing test cases, checkers, scoreboards, and coverage models
• Experience collaborating with Design, Architecture, Firmware, and Post-Silicon teams
• Experience collaborating closely with Design, Architecture, Firmware, and Post-Silicon teams
• Proven experience supporting successful ASIC/SoC tapeouts
• Bachelor’s or Master’s Degree in Electrical Engineering, Computer Science, or related field
• Must be able to work onsite 5 days/week in Silicon Valley

If interested and QUALIFIED , please send resume in Microsoft Word format to: View email address on ziprecruiter.com

Etech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.