Senior ASIC DFT DV Engineer (Hybrid)
$167.7k - $245.2kCisco Systems
The application window is expected to close on: 11/12/2026This is a hybrid role with three days per week at Cisco’s San Jose locationMeet the TeamThe Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.Your ImpactResponsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the designOwn the MBIST methodology across the Silicon One portfolio, driving unified, high-quality standards for memory testing.Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market for future silicon.Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. Minimum QualificationsBachelor’s in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years) of experience.Prior experience in test planning based on complex design specification Experience debugging using DVE/Verdi.Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.Experience with TCL, Python or Perl.Preferred qualificationsExperience in Verilog/SVExperience addressing memory failure correlation in productionExperience in silicon testing and Automatic Test Equipment (ATE)Experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent).Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by CiscoNon-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employeesExempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the nextAdditional paid time away may be requested to deal with critical or emergency issues for family membersOptional 10 paid days per full calendar year to volunteerFor non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; andOnce performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.The applicable full salary ranges for this position, by specific state, are listed below:New York City Metro Area:$167,700.00 - $282,000.00Non-Metro New York state & Washington state:$149,100.00 - $250,900.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.Job SummaryJob number: 2027869Profession: Product and Engineering
$167.7k - $245.2k
...expected to close on: 11/12/2026 This is a hybrid role with three days per week at Cisco's... ...to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening... ...Bachelor's in Electrical Engineering or equivalent with at least 7+ years (or...SeniorFull timeTemporary workLocal areaFlexible hours3 days per week$168k - $264.5k
...us today. Design-for-Test Engineering at NVIDIA works on groundbreaking... ...creative solutions for DFT architecture, verification and... ...architecture, chip architecture, ASIC design, verification, CAD, VLSI... ...we want to hear from you! #LI-Hybrid Your base salary will be determined...SeniorFull time$186.9k - $267.7k
...expected to close on: 11/12/2026This is a hybrid role with three days per week at Cisco’s... ...to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening... ...program to meet local requirements.Job SummaryJob number: 2027718Profession: Product and EngineeringSuggestedFull timeTemporary workLocal areaFlexible hours3 days per week- Palo Alto Networks, Inc. is seeking a Senior/Lead ASIC Emulation Engineer to drive emulation architecture, verify complex SoCs, and bridge hardware design with software bring-up. You will collaborate with Design, Verification, and Software teams, build scalable emulation...Senior
$136k - $218.5k
...world. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team.... ...checking/FV. Understanding of DFT logic and experience with DFT timing closure... ...autonomous, we want to hear from you. #LI-Hybrid Your base salary will be determined based...Senior- ...Hewlett Packard Enterprise invites a Senior ASIC Verification Engineer to join our dynamic team in Sunnyvale, CA on a hybrid schedule requiring ~2 days in office weekly. You will design, verify and validate VLSI blocks, build test benches in SystemVerilog/UVM, and collaborate...SeniorWork at office
- Hewlett Packard Enterprise Development LP is seeking a Senior ASIC Verification Engineer to lead VLSI verification efforts in a hybrid work model. You’ll design, validate and optimize complex ASIC blocks, mentor engineers, and collaborate with SW and logic teams to ensure...Senior
- Hewlett Packard Enterprise is seeking a Senior ASIC Verification Engineer to shape verification strategy for complex VLSI blocks in a hybrid work setting in California. The role leads teams, designs testbenches, and collaborates with SW and design peers to ensure robust...Senior
$186.9k - $267.7k
...application window is expected to close on: 11/12/2026 This is a hybrid role with three days per week at Cisco’s San Jose location... ...development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug...Full timeTemporary workLocal areaFlexible hours3 days per week$167.7k - $245.2k
...definition, architecture and design and verification of high performance ASICs• Owns complex or multiple functional areas• Develops reusable... ...ASIC and Apps, with limited external scope• Leads design and DV work by solving block level issues and participates in chip level...SeniorFull timeTemporary workLocal areaFlexible hours$120k - $220k
...our overall quality of life. We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible... ...experience in Design-for-Test (DFT) for complex digital ASICs or SoCs • Hands-on experience with industry-standard...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shift$168k - $264.5k
As a Senior DFT Engineer - Post-Silicon , you will take pioneering DFT capabilities beyond implementation—connecting silicon behavior, test... ...real passion for technology, we want to hear from you! #LI-Hybrid Your base salary will be determined based on your location,...Senior- ...precision that drives great outcomes. Your Career As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution,... ...You will define emulation architecture, build scalable hybrid co‑emulation environments, accelerate pre‑silicon software...SeniorFull timeCasual workWork at office
- ...qualification, reliability, and RMA testing for Silicon One ASICs, using ATE platforms and silicon debugging to ensure production... .... As part of this role you will partner with Product Test Engineering, DFT, and Design Engineering to define test strategies, analyze data...Senior
$155k - $222.6k
...:You will be in the Silicon One development organization as an ASIC Engineer, with a primary focus on Design-for-Test. You will work with Front... ...design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team...Full timeTemporary workLocal areaFlexible hours$129.4k - $207k
...Sign-In before you apply.Job Description:Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position. The successful candidate will be... ...ATE and RMA supportWorking closely with STA and DI Engineers design closure for testGenerating, Verifying & Debugging...Full timeLocal area$125.7k - $203.1k
...will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with... ...Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle. You will: Implement...Full timeTemporary workWork experience placementInternshipLocal areaFlexible hours- ...ContractPosted: 2026-10-06Deadline: 0001-01-01Our client is seeking a Senior ASIC Verification Engineer to join their team. As a Senior ASIC Verification Engineer... ...be part of the engineering organization supporting the DFT and ASIC verification efforts for next-generation coherent...SeniorTemporary workFor contractorsImmediate startRelocationFlexible hours
- Job description Senior DFT EngineerMoTek Technologies has an immediate opening for a Senior DFT Engineer:The ideal candiate will be responsible for DFT flows and implementation Run RTL, gate, and gate with SDF simulations to confirm correct functionality of DFT logic....SeniorImmediate start
$194.6k - $285.7k
...or if a sufficient number of applications are received.This is a hybrid role with three days per week at our San Jose, CA office.Acacia... ...communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/...SeniorFull timeTemporary workWork at officeLocal areaFlexible hours3 days per week$168k - $264.5k
...lasting impact on the world.NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s... ...UPF power verification is a plusExperience in netlist and DFT verification is a plusPerl/Python and C/C++ programming language...SeniorFull time$136k - $218.5k
...a lasting impact on the world.NVIDIA is seeking a Senior ASIC Compose Verification Infrastructure and Tools Engineer to advance the systems that qualify, integrate, and... ...driving efficiency gains outside your core RTL or DV tasks.Strong curiosity about how complex systems...SeniorFull time$136k - $218.5k
...NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading GPUs. This position offers the... ...processor pipeline verification is desirable. #LI-Hybrid Your base salary will be determined based on your location...Senior$168k - $264.5k
We are now looking for a Senior DFT Methodology Engineer! As a Senior DFT Methodology Engineer, you will architect and develop the test methodologies that make our next generation of silicon testable, debuggable, and secure from the very first bring-up. NVIDIA has crafted...SeniorFull time- ...balance and flexibility through our Hybrid Work Model.Job DescriptionKey... ...with Firmware and Software Engineers to ensure seamless integration... ...highly motivated and hands-on Senior Hardware Engineer to play a... ...manufacturing (DFM), design-for-test (DFT), and product lifecycle...SeniorFull timeContract workFor subcontractorLocal areaRemote work
- ...software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software... ...exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is hiring a Senior ASIC Verification Engineer with advanced...SeniorFull timeRemote workFlexible hours
- ...Cisco's Silicon One team is seeking an ASIC Engineer focused on Design-for-Test. You will collaborate with Front-end RTL and backend physical design to drive DFT requirements early in the design cycle as we craft next-generation networking chips. The role emphasizes post...
$138k - $190k
...Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every... ...advance our quantum technology initiatives, we are seeking a Senior Quantum Engineer, Hybrid Interconnect to pioneer technologies for scaling quantum...SeniorFull time- ...Job Description Job Description POSITION: Senior DV Engineer Who We Are: Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside...SeniorRemote work
$167.7k - $245.2k
...This is an hybrid position with approximately 3+ days in office in San Jose, California,... ...Meet the Team As a Failure Analysis Engineer, you will be part of the Quality and Reliability... ...group, performing failure analysis of ASIC products. Should have a passion for...Full timeTemporary workWork at officeLocal areaFlexible hours
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