Silicon IP Design Management Solution Engineer (Austin)

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.THE ROLE: This is a great opportunity for a seasoned engineer to develop and implement a world-class IP-Design Management Platform in a fast-paced production environment on the cutting edge of modern technology! The goal of our Central CAD team at AMD is to determine a set of standards and techniques for designing chips with the highest performance, lowest cost, and lowest power usage. We then automate these best practices into a design flow for efficiency and consistency, and work with various design teams to put the flow to use in constructing next-generation GPUs, CPUs and APUs with industry-standard EDA software tools. THE PERSON:You are a highly motivated and proactive individual who is passionate about silicon design infrastructure, project management, and solving complex design milestone problems. You are a team player with excellent communication and collaboration skills, working with other individuals, teams, and business units across different sites and time zones. You have strong analytical, organizational, and problem-solving skills. You are detail-oriented, eager to learn, and ready to take on various central platform challenges. KEY RESPONSIBLITIES:Develop, implement and deploy a world-class IP-Design Management PlatformCollaborate with project teams on their milestone deliveries and leverage the new IP-Design Management PlatformDemonstrate ownership through steady stewardship — maintaining the platform, supporting its users, and improving the platform upon the stakeholder’s feedbackPREFERRED EXPERIENCE:Experience with Silicon IP integration at SOC level is preferredExperience with Silicon IP life cycle management is preferredExperience with Silicon IP and IP-reuse: design, implementation, and productizationExperience with scripting and automation (Python, Ruby, Perl, Make, Tcl, shell scripts, or similar)Experience with version control systems (Perforce, Git, Artifactory, or similar)Experience with working with EDA vendors Experience with Linux/Unix system administrationExperience with silicon design environmentsDemonstrated experience with use of AI tools (Claude, ChatGPT, GitHub Copilot, or similar) to enhance productivity and automate workflowsACADEMIC CREDENTIALS:Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Austin, Tx #LI-HYBRID#LI-PA1This role is not eligible for visa sponsorship.Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.