Senior ASIC DFT Emulation Lead
Jobleads-US
Cisco Systems in San Jose, CA is seeking an ASIC DFT - Emulation Technical Lead to architect state‑of‑the‑art emulation environments and drive pre‑silicon testing for the Silicon One family.
You will collaborate with front‑end RTL, physical design, and ATPG teams to troubleshoot issues, validate MBIST, JTAG, and scan architectures, and ensure high‑quality post‑silicon pattern conversion for next‑generation hardware platforms.
#J-18808-Ljbffr Jobleads-USVacancy posted 13 hours ago
Similar jobs that could be interesting for youBased on the Senior ASIC DFT Emulation Lead in San Jose, CA vacancy
- ...verification leader to set vision and strategy for ASIC verification across multiple programs. You will mentor teams, lead architecture of scalable verification... ...quality. Deep expertise in SystemVerilog/UVM and emulation is required. This role offers growth opportunities...SuggestedLocal area
- Palo Alto Networks, Inc. is seeking a Senior/Lead ASIC Emulation Engineer to drive emulation architecture, verify complex SoCs, and bridge hardware design with software bring-up. You will collaborate with Design, Verification, and Software teams, build scalable emulation...Senior
- ...Cisco Systems in San Jose is seeking a seasoned Package Layout Team Leader to guide a skilled layout group for advanced ASIC packaging. You will mentor engineers, drive complex layout activities, and collaborate with cross‑functional teams across design, SI/PI, and manufacturing...Senior
- Palo Alto Networks is seeking a Senior/Lead ASIC Emulation Engineer to drive execution, verification, and validation of high-complexity network security processors on state-of-the-art emulation and FPGA prototyping platforms. You will bridge pre-silicon hardware design...Senior
$168k - $264.5k
We are now looking for a Senior ASIC Design Engineer to join our DFT team!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel...SeniorFull timeNvidia
Santa Clara, CA2 days ago- ...Analysis (STA) leader to shape the timing closure for high-performance ASICs and TPU integration. You will drive timing constraints, margins, and ECOs across large compute designs and collaborate with RTL, DFT, and architecture teams to meet tight deadlines. The role...Senior
- Eridu is seeking a hands-on ASIC Design Verification Lead to own verification strategy, infrastructure, and closure for high-performance networking silicon. This senior role requires deep expertise and practical hands-on work beyond management in a fast-moving startup....Senior
- ...Block/Core/SOC, and develop functional coverage. The role requires deep SystemVerilog expertise, UVM/VMM, and a track record of completing ASIC projects from architecture to tape-out, plus mentoring teammates and leading verification strategy reviews. #J-18808-LjbffrSenior
Broadcom Inc.
San Jose, CA1 day ago $182.36k - $273.2k
...a place to thrive, learn, and lead. Your Team, Your ImpactMarvell’... ...develops advanced, industry-leading ASICs for the hyperscale data center,... ...— and we are looking for a senior experienced technical leader to... ...analog design, digital design, DV, DFT, physical design, STA, firmware...SeniorPermanent employmentFull timeWork from homeMarvell
Santa Clara, CA3 days ago- ...Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team. You will architect testability solutions for large-scale ASICs and drive DFT strategies from RTL to silicon bring-up. Responsibilities include achieving high...Senior
- ...Cisco Systems, Inc. is seeking an experienced engineer to lead test planning and design-for-test development for advanced silicon platforms. You will craft test benches, verify DFT architectures, and collaborate with design and PD teams to implement robust in-system test...Senior
- ...time problem‑solving, stronger relationships, and the kind of precision that drives great outcomes. Your Career As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution, verification, and validation of high‑complexity network security...SeniorFull timeCasual workWork at office
Palo Alto Networks, Inc.
Santa Clara, CA4 days ago $232k - $368k
...amplify human imagination and intelligence.We are seeking an ASIC Chip Manager to help drive development of future SoC... ...as coordinate the activities of IP design, integration, DFT, physical design, VLSI, emulation, software, and operation teams to ensure successful...SeniorFull timeNvidia
Santa Clara, CA1 day ago$167.7k - $245.2k
...digital world.Your ImpactResponsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the designOwn the MBIST methodology across...SeniorFull timeTemporary workLocal areaFlexible hours3 days per weekCISCO Systems
San Jose, CA2 days ago- ...drives qualification, reliability, and RMA testing for Silicon One ASICs, using ATE platforms and silicon debugging to ensure production... ...part of this role you will partner with Product Test Engineering, DFT, and Design Engineering to define test strategies, analyze data,...Senior
020 Cisco Systems, Inc.
San Jose, CA1 day ago - ...us on this journey. Job DescriptionThe Senior FPGA/Emulation Validation Engineer position is your opportunity... ...to join one of the industry’s leading companies in platform security management... ...with the Architecture, Verification, ASIC Design and Software teams. KEY RESPONSIBILITIES...Senior
Axiado Corporation
San Jose, CA23 hours ago $136k - $218.5k
...world.We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing... ...doing:Drive Timing Analysis and Closure: Lead the timing analysis and closure processes... ...equivalence checking/FV.Understanding of DFT logic and experience with DFT timing...SeniorFull timeNvidia
Santa Clara, CA3 days ago- ...Palo Alto Networks, Inc. is seeking an experienced ASIC design professional to own frontend design from spec to silicon bring-up for... ...SystemVerilog RTL, and verifying blocks through simulation, emulation, and formal methods, with a focus on robust, scalable designs....Senior
$167.7k - $245.2k
...world. Your Impact Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design. Collaborate with the design/...SeniorFull timeTemporary workLocal areaFlexible hours3 days per week- ...About the job Senior ASIC Verification Engineer (AI Hardware) Senior ASIC Verification... ...phases Partner with FPGA and emulation teams to support early prototyping and validation... ...~ Experience working with leading EDA toolchains (e.g., Cadence, Synopsys,...SeniorRemote workVisa sponsorship
4 Staffing Corp
San Jose, CA4 days ago $136k - $218.5k
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and... ...RTL information to GPU, CPU and SOC verification team, timing and DFT teams.Get involved in end-to-end cycle of ASIC execution starting...SeniorFull timeWork experience placementNvidia
Santa Clara, CA4 days ago$168k - $264.5k
...the world.NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s leading inference accelerator. This position offers... ...verification is a plusExperience in netlist and DFT verification is a plusPerl/Python and C/C++...SeniorFull timeNvidia
Santa Clara, CA4 days ago- ...processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD... ...their impact.You're an experienced ASIC/FPGA design engineer who has delivered... ...optimization techniquesManufacturing test and DFT methodologiesSilicon bring-up and...Senior
AMD
San Jose, CA3 days ago $136k - $218.5k
...interconnect/cache/core design is desirable.Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.Strong communication and interpersonal skills are required along with the ability to work in a dynamic...SeniorFull timeNvidia
Santa Clara, CA1 day ago$136k - $218.5k
...inventiveness and intelligence.We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and... ...debugging capability and problem-solving skills.Background in DFT timing closure for various modes e.g. scan shift and capture, transition...SeniorFull timeShift workNvidia
Santa Clara, CA23 hours ago$168k - $264.5k
...passionate about DGX systems connecting multiple ASIC chips together, FPGA prototyping, and hardware emulation? Are you interested in pushing the boundaries of innovation... ...and emulation platforms. We are now looking for a Senior Systems Prototyping and Emulation Engineer to join...SeniorFull timeNvidia
Santa Clara, CA23 hours ago$136k - $218.5k
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design... ...to design and implement the world’s leading SoC's and GPU's. This position offers the... ...verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring...SeniorFull timeNvidia
Santa Clara, CA4 days ago- ...designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to... ...ROLE:The Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support...
AMD
Santa Clara, CA4 days ago $129.2k - $209k
...As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our... ...products meet or exceed industry-leading requirements for features, performance, and... ...diverse platforms including simulation, emulation, formal verification, and silicon validation...SeniorFull timeCasual workWork at officePalo Alto Networks
Santa Clara, CA1 day ago- ...Deadline: 0001-01-01Our client is seeking a Senior ASIC Verification Engineer to join their team.... ...engineering organization supporting the DFT and ASIC verification efforts for next-... ...Range: $50 - $55/hr on W2What's the Job?Lead implementation of SSN-based test flow DFT...SeniorTemporary workFor contractorsImmediate startRelocationFlexible hours
Experis
San Jose, CA2 days ago
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Senior ASIC DFT Emulation Lead. Be the first to apply!
Related searches
- senior business development San Jose, CA
- american senior communities San Jose, CA
- senior devops engineer remote San Jose, CA
- senior information technology project manager San Jose, CA
- senior vmware engineer San Jose, CA
- sr electrical engineer San Jose, CA
- sr marketing manager San Jose, CA
- senior dynamics crm developer San Jose, CA
- senior development executive San Jose, CA
- senior cost engineer San Jose, CA