Senior STA Lead for High-Performance AI ASICs
Google is seeking an experienced Static Timing Analysis (STA) leader to shape the timing closure for high-performance ASICs and TPU integration. You will drive timing constraints, margins, and ECOs across large compute designs and collaborate with RTL, DFT, and architecture teams to meet tight deadlines. The role emphasizes cross-team collaboration, scalable STA methodologies, and the delivery of robust timing sign-off for next-generation TPU hardware, with a strong focus on silicon accuracy and #J-18808-Ljbffr Google
Vacancy posted 3 days ago
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