Senior FPGA Engineer

Responsibilities Own projects - driving project progression from inception, requirements, architecture, design entry, timing closure and verification Partner closely with the Low Latency, Trading and other teams to foster and develop ideas that enhance performance Develop and maintain RTL in Verilog/SystemVerilog Write and maintain verification environments Design optimization for timing closure Develop and maintain project documentation Qualifications 10+ years of experience in FPGA or ASIC digital logic design – network traffic experience a strong plus Deep Verilog/SystemVerilog or VHDL skills Solid grasp of static timing analysis, synthesis, and place-and-route tools Familiarity with algorithms, data structures, and verification/unit testing workflows Python and Bash scripting fluency Enthusiasm for collaboration with other FPGA team members as well as members from software and trading teams Open mindedness for novel development approaches and architectures Bachelor's degree in Computer or Electrical Engineering, or related field; master's degree a plus The ability to react quickly and accurately to rapidly changing market conditions, including the ability to quickly and accurately respond and/or solve math and coding problems are essential functions of the role In accordance with Illinois Equal Pay Act, the minimum base salary starts at $145,000. Exact compensation offered may vary based on many factors including, but not limited to, the candidate's experience, qualifications, and skill set. This role is also eligible for a discretionary performance bonus as part of the total compensation package and includes a comprehensive benefits package that may encompass employer-paid medical, dental, vision, retirement contributions, paid time off, and other benefits. The minimum base salary herein was determined in good faith by Akuna Capital LLC. #J-18808-Ljbffr Akuna Capital