Senior Design Verification Engineer
$119.8k - $234.7kMicrosoft Corporation
Job ID: 200044483Posted: 2026-07-24Location: United States, California, Mountain ViewSalary: USD $119,800 - $234,700 per yearEmployment type: Full-TimeWork site: 3 days / week in-officeRole type: Individual ContributorTravel: Less than 25%Profession: Hardware EngineeringDiscipline: Silicon EngineeringCompany: MicrosoftOverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI Silicon Engineering (AISiE) SoC Design Verification team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Design Verification Engineer to join the team. #SCHIE ResponsibilitiesBuid, validate and automate emulation models with constant improvement in runtime efficiency. Preferred platforms include Zebu and Palladium. Develop complex verification environments and test suites, including pre-silicon functional verification at the block, chip, and system levels, reference modeling, and post-silicon validation. Collaborate with architects and design engineers to define verification plans, including strategy, test environments, and requirements for IP/Subsystem/SoC-level verification. Create and drive comprehensive test plans and develop tests to ensure full feature coverage. Design and implement technical solutions to address complex design and quality challenges. Develop verification components such as scoreboards, sequences, constrained random tests, assertions, and functional coverage models. Triage and debug failures in testbenches, simulations, and emulation environments. Develop Makefiles and automation scripts to enable scalable and efficient verification flows. Apply Agile methodologies, including participation in code reviews, sprint planning, and continuous integration practices. Collaborate effectively with cross-functional teams across multiple sites and geographiesQualificationsRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.Preferred Qualifications: 6+ years of experience in creating emulation and simulation environments, developing tests, and debugging for multiple silicon IP's or systems. 3+ years’ industry experience of chip and/or computer architecture. 3+ years industry experience in Verilog, C/C++, and scripting language such as Python, Ruby or Perl CPU or Graphics core verification experience Experience with hardware emulation or FPGAs. In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure. Experience with hardware design for embedded systems. Firmware development, with secure and non-secure boot flow. Design experience or ability to write synthesizable code. Software development experience. Communication skills. Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
$163k - $237k
Develop verification plans and test plans for digital intellectual properties (IPs) and subsystems... ...:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science... ...and subsystems.Experience working with design verification (DV) testbenches or...SeniorWorldwide$163k - $237k
Verify designs using verification techniques and methodologies.Work cross-functionally to debug failures and verify the functional correctness... ....Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field,...SeniorWorldwide$163k - $237k
...and programmable IPs.Drive verification excellence by implementing sophisticated... ...and coverage models designed to track, manage, and close... ...guide junior verification engineers on design verification (DV)... ...efficiency, and integration.As an Senior ASIC Design Verification...SeniorWorldwide- ...millions of patients worldwide.We’re a team of engineers, clinicians, and innovators united by... ...from test-planning to closing verification using coverage metricsHands-on testbench development UVMWork closely with the design team to review specifications and architecture...SeniorLocal areaWorldwideFlexible hours
$163k - $237k
Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog and UVM...SeniorWorldwide$163k - $237k
Lead CAD methodology engineers to provide support for chip Design Verification (DV) teams, and manage and mitigate support issues for tool flows.Partner with chip... ...its integration within AI/ML-driven systems. As a Senior Engineer within Google's silicon team, you will...SeniorWorldwide- ...subsystem and standard interfaces using SystemVerilog/UVM. Develop verification plans, UVM testbenches, test cases, assertions (SVA), and... ...management, and exception handling. Execute regressions, debug RTL/design issues, and drive functional and code coverage closure....Senior
$136k - $218.5k
We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel...SeniorFull time$136k - $218.5k
NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to...SeniorFull timeWork experience placementRemote work$175k - $280k
...the ultimate goal of enabling human life on Mars.SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience... ...& BENEFITS: Pay range: Design Verification Engineer /Senior: $175,000.00 - $280,000.00/per year Your actual level and...SeniorPermanent employmentTemporary workWorldwideWeekend work$164.47k - $311.89k
Job Details:Job Description: About the RoleIntel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive...SeniorFull timeInternshipLocal areaImmediate startShift work$124k - $208.4k
...market segments) consumed by millions of people around the world. Come build with us!Role and ResponsibilitiesAs a Senior GPU Design Verification Engineer - GCDV, you will contribute to the verification of top-level graphic core for Samsung’s next-generation mobile GPU....SeniorHourly payFull timeRelocation$167.7k - $245.2k
...help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able... ..., experiment more, and work quickly. As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary...SeniorFull timeTemporary workLocal areaFlexible hours$250k - $300k
...ultra high-speed inference.Key ResponsibilitiesWork with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.Develop and implement verification strategies, detailed tests and coverage plans based on micro-...Senior- ...possibilities of AI. Location:Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.The role:Senior Staff Design Verification Engineer What you will do:We want to build a company and a culture that sustains the tests of time. We offer the candidate...Senior3 days per week
- ...Experience with Verilog, System Verilog, and modern verification libraries like UVM 10+ years of ASIC design verification experience Experience / Background... ...TCL is a plus Collaborate with architects, hardware engineers, and firmware engineers to understand the new...Senior
$134.39k - $201.3k
...principle — sharing reusable components, verification environments, and knowledge across all... ...silicon.As part of the COE, you will design, verify, and deliver IP subsystem building... ...
