Senior SoC Verification Architect (UVM & Formal)
Silicon Labs
Silicon Labs is seeking a Senior Staff Digital Verification Engineer based in Austin, TX. The role involves executing verification plans using simulation and formal verification techniques while collaborating with cross-functional teams. Candidates should have over 10 years of design verification experience, a Bachelor's or Master's degree in Electrical/Computer Engineering, and expertise in Verilog, SystemVerilog, UVM, and C/C++. Join Silicon Labs to work on innovative low-power wireless connectivity technology. #J-18808-Ljbffr Silicon Labs
Vacancy posted 4 days ago
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