ASIC DFT Engineer

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post silicon debug, and yield improvement to meet the product test metrics. It involves working with the Physical Design and STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.Responsibilities:Understanding Broadcom and customer DFT feature requirements, and DPPM goals and defining appropriate DFT specifications for the ASICImplementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integrationPattern generation and verification at chip level, rapid bring-up at ATE and RMA supportWorking closely with STA and DI Engineers design closure for testGenerating, verifying, and debugging test vectors before tape releaseValidating and debugging test vectors on ATE during the silicon bring up phaseAssisting with silicon failure analysis, diagnostics, and yield improvement effortsInterfacing with the customer, physical design and test engineering/manufacturing teams located globallyWorking closely with I/P DFT engineers and other stakeholdersDebugging customer returned parts on the ATEInnovating newer DFT solutions to solve testability problems in 3nm and beyondAutomating DFT and test vector generation flowsSkills/Experience:Bachelors and 17+ years of related experience; or Masters degree and 15+ years of related experienceStrong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)Logic BIST design and debug experienceWell-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)Experience in Verilog coding, testbench generation and simulationMemory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)Boundary scan verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6Basic knowledge Test-STA and constraintsStrong background on IEE1687, IJTAG, ICL, and PDL The ability to work in a multi-disciplined, cross-department environmentSolid knowledge in analog and digital circuit design, and device physics fundamentalsGood understanding of Si processing, logical and physical synthesis, and transistor reliability principlesExcellent problem solving, debug, root cause analysis and communication skillsStrong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metricsProject management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.Experience working on ATE is a plusExperience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification, and silicon debug is a plusExperience working on Tessent SSN is a plusCompensation and BenefitsThe annual base salary range for this position is USD 167,500.00 To USD 268,000.00As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.SummaryLocation: USA-California-San Jose-1320 Ridder Park DriveType: Full time