ASIC DFT Technical Leader- MBIST
$210.6k - $305.1kCisco Systems
The application window is expected to close on: 09/01/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.Meet the team: The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. You will be part of the Silicon One development organization as an ASIC Technical Lead- MBIST engineer. As a member of this team you will be involved in crafting cutting edge next generation networking chips.Your Impact:You will be leading the MBIST methodology in silicon one chips.Design & implement robust and reusable MBIST architecture. Spec comprehensive MBIST architecture and implementation agnostic to technology and tools.MBIST requirement definition for advanced technology nodes & advanced tech packages.Minimum Qualifications:Bachelors in Electrical engineering with at least 12+years (or Master's with 10+ years) of experience in ASIC DFT.Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.Prior experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent).Scripting skills (Python, TCL, Perl) for automation of test generation and analysis.Strategic Skills: Ability to plan and execute complex test strategies, excellent communication skills for cross-team collaboration, and a focus on silicon quality and yield improvement.Preferred Qualifications:Experience in Verilog/System Verilog.Experience addressing Memory failure correlation in production.Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by CiscoNon-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employeesExempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the nextAdditional paid time away may be requested to deal with critical or emergency issues for family membersOptional 10 paid days per full calendar year to volunteerFor non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; andOnce performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.The applicable full salary ranges for this position, by specific state, are listed below:New York City Metro Area:$210,600.00 - $350,800.00Non-Metro New York state & Washington state:$189,300.00 - $312,200.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.Job SummaryJob number: 2018240Date posted : 2026-07-15Profession: Product and EngineeringEmployment type: Full time
$186.9k - $267.7k
...developing and testing some of the most complex ASICs being developed in the industry. Your ImpactAs an ASIC DFT - Emulation Technical Lead, you will play a critical role in... ...plan execution, and validate complex scan, MBIST, and JTAG architectures on platforms like Palladium...SuggestedFull timeTemporary workLocal areaFlexible hours$186.9k - $267.7k
...revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.Your Impact:As a technical leader, you will own and drive end-to-end DFT flow architecture, building and maintaining scalable CAD infrastructure that...SuggestedFull timeTemporary workLocal areaFlexible hours$186.9k - $267.7k
...Join us to power the future of the digital world. Your Impact:You will be in the Silicon One development organization as an ASIC Technical Leader- DFT. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT...SuggestedFull timeTemporary workLocal areaFlexible hours- ...help you find the best job for you. Role: Lead ASIC DFT Engineer Location: Remote Duration: 1... ...ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation...SuggestedPermanent employmentContract workRemote work
- Title - Lead ASIC DFT Engineer Location - San Jose, CA. Job Description Experience 10+ years of hands-on... ...ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation...Suggested
$186.9k - $267.7k
...developing and testing some of the most complex ASICs being developed in the industry. Your ImpactAs an ASIC Technical Lead, you will stand at the absolute forefront of... .... By driving cutting-edge Design-for-Test (DFT) strategies and pioneering custom IP solutions,...Full timeTemporary workLocal areaWorldwideFlexible hours- ...Engineers Land Roles at Top U.S. Firms Required Skills & Qualifications Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and MBIST MBIST Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route...Contract work
$214.1k - $309.8k
...Your ImpactThis position provides high-level technical leadership for the Silicon One organization, bridging the gap between advanced DFT architecture, silicon quality, and high-... ...hardware environments.Deep knowledge of the full ASIC development lifecycle, specifically within...Full timeTemporary workWork at officeLocal areaFlexible hours$122.44k - $232.19k
...supply chain.Position OverviewWe seek a DFT Application Engineer to provide technical support to Intel Foundry Services... ...quality improvements in ASIC DFT/DFM and ATPG validation methodology... ...implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design...Full timeInternshipLocal areaImmediate startShift work$186.9k - $267.7k
...the digital world.Your ImpactLead the planning and execution of ASIC verification for complex networking SoCs, ensuring high-quality... ...multiple IPs and subsystem-level verification efforts.Provide technical leadership and mentorship to verification engineers, promoting...Full timeTemporary workLocal areaFlexible hours$143.8k - $230k
...high-impact role, you will be the primary technical anchor responsible for the top-level... ...+ years of direct industry experience in ASIC/SoC digital design, with a proven track record... ...custom interconnects).Familiarity with DFT (Design for Test) planning, including scan...Full timeLocal area$186.9k - $267.7k
...Join us to power the future of the digital world. Who You'll Work With:You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-...Full timeTemporary workWork at officeLocal areaFlexible hours$220k - $250k
...micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep... ...Physical Design (PD) STA / Timing / DFT teams Ensure high RTL quality via:... ...aware sims) Knowledge of DFT (scan, MBIST, compression) Experience with high-...$183k - $247.6k
...and software stacks enable us to take on technical challenges that have never been seen before... ...technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new... ...SOC, ensure correct clock/reset/functional/DFT signal routing- Analyze design, microarchitecture...Local areaFlexible hours$186.9k - $267.7k
...post silicon validation tests in the lab.Minimum QualificationsBachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or...Full timeTemporary workLocal areaFlexible hours$210.6k - $305.1k
...flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.Proficiency in low-power design...Full timeTemporary workLocal areaFlexible hours- ...SystemVerilog/Verilog (for correlating failures to rtl if needed) Good to have (not critical): * Scan insertion * RTL DFT Verification capability (MBIST, clocking etc..) * DFT DRC (spyglass) \nCompany Description Who We Are: Quest Global delivers world-class end-...
- ...closely with Architecture, RTL, Verification, DFT, Physical Design, STA, and Silicon... ...integration, timing closure methodologies, and full ASIC development flow from architecture through... ...including: Scan insertion MBIST LBIST JTAG/Boundary Scan At...Full time
$182.36k - $273.2k
...closely with the architecture, floor planning, backend, verification, DFT, STA teams, and other cross-functional teams to produce high-... ...PCIe, and D2D.Experience in micro-architecture of complex custom/ASIC products, focusing in one or more of the following areas: NPU,...Permanent employmentInternshipWork from home$171.6k - $245k
...track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks... ...platform.Your ImpactIn this highly visible role as Compute Hardware Technical Leader, you will be part of a dynamic and passionate team working on...Full timeTemporary workWork at officeLocal areaFlexible hours$163k - $236k
Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high...Worldwide- ...a seasoned Hardware Engineer to create and optimize designs for cutting-edge ASIC products. The role involves collaboration across teams to enhance yield and quality while providing technical leadership in design evaluations. Candidates must possess a Master's degree in...
$186.9k - $267.7k
...TeamCisco Silicon One is the center of Cisco’s ASIC design and is driving the development of... ...). Additionally, you’ll collaborate with leaders across different functions within the... ...us.Your ImpactAs a Software Engineering Technical Leader for the Silicon One Customer Engineering...Full timeTemporary workLocal areaFlexible hours$240k - $333k
...in Electrical Engineering, Computer Engineering, or a related technical field.12 years of experience in design verification.Experience... ...architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Technical Lead, you will define how Google...WorldwideShift work$157.3k - $212.8k
...world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right...InternshipLocal areaWork from homeFlexible hours$171.6k - $245k
...sufficient number of applications are received.Hardware Engineering Technical Leader (onsite) - 2014979*position requires onsite work activity at... ...& Root Cause Analysis• Debug complex issues spanning ASICs, firmware, drivers, and network OS• Perform root cause analysis...Full timeTemporary workWork at officeLocal areaFlexible hours$168.8k - $241.2k
...digital world. Your Impact Hardware design technical lead is a key member of the Cisco Purpose... ...based on Silicon One and/or merchant ASIC.Responsible for system and board level specification... ...with multiple groups including ASIC, DFT, Signal Integrity, software, Diagnostics...Full timeTemporary workLocal areaFlexible hours$152k - $230k
...to join us today.Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.What you'll be doing...Full time$177.9k - $284.7k
...functionality. Nextest engineering teams are characterized by deep technical skills working with both software and hardware. Our Engineers... ...software that directly interacts with hardware (FPGAs and ASICs)Knowledge of Windows and experience with Visual Studio requiredFamiliarity...Local areaRelocationFlexible hours- ...candidates in the range of Sr. Staff Engineer to Sr. Principle Engineer levels.DFT Architecture and ImplementationDefine and implement DFT architecture, including scan, boundary scan (IEEE 1149.1/1687), MBIST, and related features.Collaborate with design and physical design...
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