ASIC DFT Technical Leader
$186.9k - $267.7kCISCO Systems
The application window is expected to close on: 10/02/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.Meet the Team:The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact:You will be in the Silicon One development organization as an ASIC Technical Leader- DFT. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.Minimum Qualifications:Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10 years of experience.Prior experience working in the latest innovative trends in DFT, test and silicon engineering.Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTimePrior experience working with Gate level simulation, debugging with VCS and other simulators.Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687Preferred Qualifications:Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verificationDFT CAD development - Test Architecture, Methodology and InfrastructureTest Static Timing AnalysisPost silicon validation using DFT patterns.Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the designWhy Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by CiscoNon-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employeesExempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the nextAdditional paid time away may be requested to deal with critical or emergency issues for family membersOptional 10 paid days per full calendar year to volunteerFor non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; andOnce performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.The applicable full salary ranges for this position, by specific state, are listed below:New York City Metro Area:$186,900.00 - $307,800.00Non-Metro New York state & Washington state:$166,300.00 - $274,100.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.Job SummaryJob number: 2018237Profession: Product and Engineering
$214.1k - $309.8k
...will be part of the Silicon One development organization as an ASIC Technical Lead- MBIST engineer. As a member of this team you will be... ...least 12+years (or Master's with 10+ years) of experience in ASIC DFT.Prior experience with memory architectures (SRAM, DRAM, etc.)...SuggestedFull timeTemporary workLocal areaFlexible hours$186.9k - $267.7k
...'s ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your ImpactAs an ASIC DFT - Emulation Technical Lead, you will play a critical role in driving the DFT emulation strategy for Silicon One....SuggestedFull timeTemporary workLocal areaFlexible hours- ...experts can help you find the best job for you. Role: Lead ASIC DFT Engineer Location: Remote Duration: 1 year Required... ...for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST...SuggestedPermanent employmentContract workRemote work
$214.1k - $309.8k
...Your ImpactThis position provides high-level technical leadership for the Silicon One organization, bridging the gap between advanced DFT architecture, silicon quality, and high-... ...hardware environments.Deep knowledge of the full ASIC development lifecycle, specifically within...SuggestedFull timeTemporary workWork at officeLocal areaFlexible hours$186.9k - $267.7k
...revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.Your Impact:As a technical leader, you will own and drive end-to-end DFT flow architecture, building and maintaining scalable CAD infrastructure that...SuggestedFull timeTemporary workLocal areaFlexible hours$186.9k - $267.7k
...Operations, you’ll join forces with expert ASIC design teams in the Central Hardware... ...of the latest state-of-the-art trends in DFT insertion techniques, including Scan, ATPG... ...leadership across many parts of Cisco's technical entities to provide bleeding-edge solutions...Full timeTemporary workWork at officeLocal areaFlexible hours- ...elevate their impact.You're an experienced ASIC/FPGA design engineer who has delivered... ...functional area. Instead, you'll serve as a technical partner to chip leads across dynamic,... ...optimization techniquesManufacturing test and DFT methodologiesSilicon bring-up and...
$143.8k - $230k
...high-impact role, you will be the primary technical anchor responsible for the top-level... ...+ years of direct industry experience in ASIC/SoC digital design, with a proven track record... ...custom interconnects).Familiarity with DFT (Design for Test) planning, including scan...Full timeLocal area$186.9k - $267.7k
..., and work quickly. Join us to power the future of the digital world. You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional...Full timeTemporary workWork at officeLocal areaFlexible hours- ...Responsibilities: Lead implementation of SSN based test flow DFT architectures, including scan insertion, compression/decompression... ...+ 3 years of related experience Prior experience working with ASICs Prior experience in scan insertion and DFT setup, integration...
$214.1k - $309.8k
...ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your ImpactAs an ASIC DFT - Emulation Technical Leader, you will play a critical role in driving the DFT emulation strategy for Silicon One’s DFT...Full timeTemporary workLocal areaFlexible hours$192k - $278k
...integrity.Partner with internal teams (RTL, DFT, methodology, packaging) to achieve... ...route, and timing closure for high-speed ASICs across various process nodes.Experience in... ...physical sign-off, and 2.5D/3D packaging.Technical leadership experience managing execution...Worldwide$213k - $287.5k
...and software stacks enable us to take on technical challenges that have never been seen before... ...technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new... ...SOC, ensure correct clock/reset/functional/DFT signal routing- Analyze design, microarchitecture...Local areaFlexible hours$186.9k - $267.7k
...post silicon validation tests in the lab.Minimum QualificationsBachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or...Full timeTemporary workLocal areaFlexible hours- ...Silicon in the Bay Area, Austin, or Kent. You will design DSP/PHY algorithms, optimize for power and performance, and collaborate with ASIC, RFIC, and SW teams to bring pre-silicon platforms to life. Ideal candidates have 10+ years in DSP, hands-on MATLAB/Python/C/C++...
- ...Samsung Semiconductor seeks an experienced ASIC verification engineer to advance memory and AI accelerator projects at our San Jose headquarters or Folsom facility. You will contribute to verification strategy, microarchitecture reviews, and post-silicon debugging, collaborating...
$186.9k - $267.7k
...software engineering roadmap.• May lead small-to-medium features from technical design through completion.• Contribute to delivery of high-... ...and SDK development experience on NPU/DPU or networking ASICs· Experience with traffic generator tools such as IXIA & SpirentPreferred...Full timeTemporary workLocal areaFlexible hours$186.9k - $267.7k
...TeamCisco Silicon One is the center of Cisco’s ASIC design and is driving the development of... ...). Additionally, you’ll collaborate with leaders across different functions within the... ...us.Your ImpactAs a Software Engineering Technical Leader for the Silicon One Customer Engineering...Full timeTemporary workLocal areaFlexible hours$240k - $333k
...in Electrical Engineering, Computer Engineering, or a related technical field.12 years of experience in design verification.Experience... ...architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Technical Lead, you will define how Google...WorldwideShift work$176.6k - $247.3k
...world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right...InternshipLocal areaWork from homeFlexible hours$214.1k - $309.8k
...track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks... ...We are seeking a highly qualified Signal and Power Integrity Technical Leader to help us develop our next generation ASIC packaging and lead...Remote jobFull timeTemporary workWork at officeLocal areaFlexible hours- ...senior hardware validation engineer to drive validation from pre-silicon emulation through post-silicon characterization for high-speed ASICs used in data centers. The role emphasizes Python-driven test development, lab automation, and data analysis, with extensive hands...
- ...programming and collaboration with product management and architects. The position focuses on subsystems, OS-level work, and forwarding ASIC development. An onsite presence in California is expected, with opportunities to contribute to next-generation networking solutions....
$171.6k - $245k
...designing, developing, and testing some of the most complex ASICs being developed in the industry.The Cisco Service Provider Routing... ...Hardware Board Design Engineer, you will be a recognized technical leader for a product. You will apply deep hardware expertise to define...Full timeContract workTemporary workLocal areaFlexible hours$171.6k - $245k
...and collect schematicsGuide layout and routing phase of the designWrite hardware specs, develop test plans, bring up hardware with ASIC teamsDebug issues the lab using analyzers, scopesCollaborate multi-functionally with architects, developers, and vendors within Cisco...Full timeTemporary workLocal areaWorldwideFlexible hours$186.9k - $267.7k
...team! This team works on Hyperscale network and Enterprise Data Center switches based on Cisco Silicon One ASIC. This is a unique opportunity to grow your technical skills and will allow for visibility and recognition across multi-functional teams within Cisco. We value...Full timeTemporary workLocal areaFlexible hours$171.6k - $245k
...digital world. Your Impact Hardware design technical lead is a key member of the Cisco Purpose... ...based on Silicon One and/or merchant ASIC.Responsible for system and board level specification... ...with multiple groups including ASIC, DFT, Signal Integrity, software, Diagnostics...Full timeTemporary workLocal areaFlexible hours$152k - $230k
...to join us today.Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.What you'll be doing...Full time- ...NVIDIA seeks a world-class engineer to drive applied research at the intersection of AI and ASIC design. You will apply LLMs, coding agents, and agentic systems to core ASIC problems—RTL generation, verification, and PPA optimization—speeding up design cycles and delivering...
- ...of SystemVerilog/Verilog (for correlating failures to rtl if needed) Good to have (not critical): * Scan insertion * RTL DFT Verification capability (MBIST, clocking etc..) * DFT DRC (spyglass) \nCompany Description Who We Are: Quest Global delivers world...
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