Senior ASIC Timing & STA Engineer
Apple Inc.
Apple Inc. is seeking an experienced ASIC STA Engineer in Cupertino to drive timing closure across all SoC stages. You will own timing constraints, sign-off activities, and collaborate with RTL, CAD, and Physical teams to achieve timing goals. You will apply expertise in Primetime and scripting to streamline flows, improve closure reliability, and contribute to the design of next-generation Apple silicon. #J-18808-Ljbffr Apple Inc.
Vacancy posted 16 hours ago
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