ASIC Verification Engineer - SystemVerilog / UVM
PTEC Solutions Inc.
PTEC Solutions Inc. is looking for a Verification Engineer in San Jose, California. The ideal candidate has at least 4 years of experience in pre-silicon design verification and 2 years of hands-on experience with System Verilog and UVM. Responsibilities include building and maintaining testbenches and writing a variety of tests for medium-complexity design blocks. The role also involves debugging with design engineers and developing a UVM verification environment. Interested candidates should send their resume to View email address on click.appcast.io. #J-18808-Ljbffr PTEC Solutions Inc.
Vacancy posted 4 days ago
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