Senior Hardware Design & UVM Verification Engineer
TechDigital Group
An established industry player is seeking a skilled verification engineer with extensive experience in UVM and SystemVerilog. This role involves defining and implementing a comprehensive verification environment, writing test plans, and debugging RTL and gate-level netlists. Ideal candidates will have a strong technical background, particularly in high-speed serial interfaces and analog/mixed-signal IPs. Join a dynamic team where your expertise will contribute to cutting-edge projects and drive innovation in the tech landscape. If you're passionate about verification and thrive in a challenging environment, this opportunity is perfect for you. #J-18808-Ljbffr TechDigital Group
Vacancy posted 1 day ago
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