Immediate Opportunity - SerDes Design & Architecture Engineer

Job Description

Job Description

This job is posted on behalf of Steinman Recruiting Associates by Top Echelon.

A global semiconductor client in the "silicon forest" seeks a proven high-speed digital circuit designer to coach, mentor, and technically guide a small team in the architecture and design of high-speed circuits. Fast tape outs on new iterations. Exciting customer solutions for Industrial, automotive, healthcare, robotic and agricultural applications.

You will evaluate and develop architectures. Own the digital circuit design throughout the development cycle. Technically lead the design and development of complex SerDes products. Understanding of communication theory, high-speed SerDes transceiver architectures, and video/data transport. Verilog and SystemVerilog to design digital blocks, subsystems, and top‑level designs. RTL Design and Implementation. Verification and Coverage Closure. Digital Backend. Mixed‑Signal Integration. Lab & Silicon Debug. Cross‑Functional Collaboration.

Skills and experience that will get our attention:

- Demonstrated success designing, leading, and introducing products to the market.

- Design digital blocks, subsystems, and top‑level designs using Verilog and SystemVerilog.

- Develop block‑level testbenches, verify block functionality, and collaborate with verification teams to achieve full‑chip verification and coverage closure.

- Perform block and top‑level linting, CDC analysis, and power analysis. Assist with synthesis constraints and timing closure.

- Communicate closely with mixed-signal designers and verification engineers to support mixed‑signal simulations and real‑number modeling across the analog/digital boundary.

Desirable:

- PhD/MS

- SerDes Standards and Protocols

- Authoring SerDes technical standards

- Verification of mixed-signal systems with behavioral modeling.

- Automotive multi-Gigabit high-speed video, sensor, and control data.

- Matlab and design of DSP blocks, including digital filters and signal-processing algorithms.

Title: Lead - Principal Engineer - Architect

Worksite: Portland, Oregon (Hybrid). A comprehensive relocation package offered.

The base salary is open (est.~$230,00 DOE). Lucrative bonus plan. Significant RSUs. Excellent benefits package.

Highly qualified TN eligible and current H-1B visa holders are encouraged to apply.