Senior RTL Verification Engineer — SystemVerilog & UVM
Delos Data Inc
Delos Data Inc. in Silicon Valley is seeking an experienced RTL Verification Engineer to ensure the functionality of complex digital designs for ASIC/FPGA platforms. You will build robust verification environments, implement coverage-driven plans, and collaborate with RTL designers to deliver reliable silicon. The ideal candidate has hands-on SystemVerilog, UVM, and Python experience and will drive verification from planning through closure. #J-18808-Ljbffr Delos Data Inc
Vacancy posted 5 days ago
Similar jobs that could be interesting for youBased on the Senior RTL Verification Engineer — SystemVerilog & UVM in Palo Alto, CA vacancy
$163k - $236k
Lead comprehensive verification strategies and signoff for complex blocks... ...from HLS code to generated RTL.Design and maintain advanced... ...functional validation and SystemVerilog/UVM for RTL timing and system... ...verifiability and mentor junior engineers on the nuances of HLS...SeniorWorldwideGoogle
Mountain View, CA4 days ago$120k - $225k
...Design Verification Engineer We're hiring experienced Design Verification... ...engineers collaborate closely with RTL design, architecture... ...development and execution using UVM or other advanced DV... ...~ Understanding of Verilog, SystemVerilog, and UVM. ~ Proven track record...SeniorMythic
Palo Alto, CA5 days ago- Lightmatter is hiring a Design Verification Engineer in Mountain View to advance verification across digital, analog, and photonic devices using UVM and emulation. You will work with digital and photonic designers to define robust validation flows and scalable test bench...Senior
$150k - $250k
Job Title: Senior ASIC Verification EngineerJob Location: Santa Clara, CA or Boston, MACompensation... ...: ASIC/SoC Verification, RTL Verification, UVM / SystemVerilog, High-Speed Interconnects (Ethernet... ...skilled Senior ASIC Verification Engineer to join our dynamic team. This...SeniorCyberCoders
Santa Clara, CA3 days ago$136k - $218.5k
...seeking best-in-class ASIC Verification Engineers to verify the world’s leading... ...testbenchPartner closely with RTL and architecture teams to... ...requiredStrong ability with SystemVerilog, test planning, coverage closure... ...Verification Methodology (UVM), SystemVerilog checkers and...SeniorFull timeShift workNvidia
Santa Clara, CA6 days ago$220.92k - $311.89k
...across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical... ...environments using SystemVerilog Assertions (SVA) and industry... ...Collaborate with architects, RTL developers, and physical design... ....• Familiarity with UVM-based simulation environments...SeniorFull timeInternshipLocal areaImmediate startShift workIntel
Santa Clara, CA6 days ago$136k - $218.5k
...is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification... ...signoff. Debug complex RTL and verification issues and work closely... ...subsystems. ~ Strong background in SystemVerilog, UVM, constrained-random verification, and...SeniorNVIDIA Corporation
Santa Clara, CA16 hours ago- ...Verification Engineer • Develop verification environments, reference models, scoreboards, protocol... .... Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance... ...and datapath logic, including RTL and system-level debug. Preferred...SeniorNight shift
Advanced Technology Innovation
Cupertino, CA5 days ago - ...Fabric transport layer verification team is looking for a senior pre-silicon verification engineer to help verify our... ...impactPartner with architects, RTL, and firmware leads... ...random testing using SystemVerilog and UVMSolve complex,... ...in using UVM testbenches and working...Senior
AMD
Santa Clara, CA3 days ago $163k - $236k
...development process.Plan the verification of multimedia design blocks... ...with architecture and design engineers to identify important... ...environments using system verilog and UVM. Identify and implement... ...and languages (e.g., UVM and SystemVerilog).Experience with interconnect...SeniorWorldwideGoogle
Mountain View, CA2 days ago$184k - $287.5k
We are now looking for a Senior Firmware Verification and Bringup Engineer to join our Memory Subsystem Team! Widely... ...closely with system Software, RTL Design, DV, emulation, and post-... ...debugging bare-metal firmware in RTL / SystemVerilog / UVM testbenches using Verdi or...SeniorFull timeNvidia
Santa Clara, CA5 days ago$164.47k - $311.89k
...the RoleIntel is seeking a Senior Design Verification Engineer for the Silicon Chassis... ...behavior, with enough breadth in RTL, physical design, and CAD... ...methodologies including UVM, SVA, ABV, and co-... ...coding experience across SystemVerilog/UVM, C/C++, Python, and build...SeniorFull timeInternshipLocal areaImmediate startShift workIntel
Santa Clara, CA6 days ago$119.8k - $234.7k
...Hardware, and Infrastructure Engineering (SCHIE) is the team... ...infrastructure. We are looking for a Senior Silicon Design Verification Engineer to join the team... ...additional custom FPGA RTL for protocol interfaces... ...working knowledge of SystemVerilog testbenches.Experience...SeniorOngoing contractPermanent employmentWork at officeLocal areaWorldwide3 days per weekMicrosoft
Mountain View, CA6 days ago$136k - $218.5k
...world.NVIDIA is seeking a Senior ASIC Compose Verification Infrastructure and Tools Engineer to advance the systems... ...role is ideal for an RTL compose or pre-silicon... ...methodology such as UVM or similar.Strong... ...knowledge of Verilog/SystemVerilog, including RTL development...SeniorFull timeNvidia
Santa Clara, CA6 days ago$200k - $300k
...We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s... ...you will work closely witharchitects, RTL engineers, software engineers, and system... ...verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification...SeniorFlexible hoursVelaura AI, Inc.
Santa Clara, CA3 days ago$250k - $300k
...post silicon and software engineers to ensure a high-quality... ...silicon.Develop and implement verification strategies, detailed... ...including architecture, RTL design, physical design,... ...skills.Deep knowledge of SystemVerilog testbench, DPI and UVM.Excellent programming skills...SeniorCerebras Systems
Sunnyvale, CA6 days ago$153.5k - $310.5k
## Senior Design Verification EngineerApplylocations: Sunnyvale, California, United... ...** **Design Verification Engineer** with specialized... ...Build, maintain, and enhance UVM/SystemVerilog-based testbench environments... ...design concepts including RTL design, synthesis constraints...SeniorWork experience placementWork at office2 days per weekHewlett Packard Enterprise
Sunnyvale, CA4 days ago$200k
...Design Verification Engineer We are looking for talented Design Verification Engineers to help... ...will work closely with architects, RTL engineers, software engineers, and system... ...verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification...SeniorFlexible hoursAuradine
Santa Clara, CA5 days ago- NVIDIA invites a Senior Firmware Verification and Bringup Engineer to join their Memory Subsystem Team in Santa Clara. You will lead bare-metal firmware... ...firmware design/verification, proficiency with RTL/SystemVerilog/UVM and C/C++/Python, and experience with high-speed...Senior
$163k - $236k
Plan the verification of complex digital design blocks by understanding... ...interacting with design engineers to identify important... ...verification environments using SystemVerilog and UVM.Identify and write all types... ...verifying digital logic at RTL using SystemVerilog/UVM for...SeniorWorldwideGoogle
Sunnyvale, CA4 days ago$164.9k - $223.1k
ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV Company: The Boeing... ...Inheritance and Polymorphism, and leverage UVM to create drivers, monitors,... ...functional verification using SystemVerilog with delivery/release of...SeniorPermanent employmentWork experience placementInterim roleRelocationVisa sponsorshipWork visaFlexible hoursShift workDay shift- Apple Inc. in Santa Clara is seeking a senior hardware verification engineer to own the CDC/RDC sign-offs for CPU designs, collaborate with RTL and DV teams, and drive robust STA... ...domains. The role requires deep Verilog/SystemVerilog expertise, experience with CDC/RDC,...Senior
$160k - $240k
...the craft seriously. What we need: An experienced RTL Verification Engineer responsible for ensuring the functionality, correctness,... ...The ideal candidate has deep hands‑on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows...Remote workDelos Data Inc
Palo Alto, CA5 days ago$136k - $218.5k
NVIDIA is seeking an exceptional Senior SoC ASIC Verification Engineer to confirm the functionality of the world... ...generation SoCs.Collaborate with architects, RTL designers, FPGA, and emulation... ...: C++, Object-Oriented Programming, UVM, System Verilog.Familiarity with verification...SeniorFull timeWorldwideNvidia
Santa Clara, CA2 days ago$168k - $264.5k
...on the world.NVIDIA is looking for a Senior Verification Engineer to join our Emulation division onsite... ...Estimation, SpeedBridges, Accelerated UVM Testbenches).Bring up SOCs on... ...proficient in Verilog and/or VHDL, C/C++ and SystemVerilog.Experience with UVM verification...SeniorFull timeWorldwideFlexible hoursNvidia
Santa Clara, CA6 days ago$168k - $264.5k
...best work. We are seeking a skilled Senior Verification Engineer to join our Display Team and help verify... ...and performance), and build scalable UVM-based infrastructure; leverage... ...experience.Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a...SeniorFull timeNvidia
Santa Clara, CA3 days ago$136k - $218.5k
...NVIDIA VLSI team is looking for a Senior Cell Modeling and Verification Engineer with strong experience in hardware... ...the NVIDIA products.Use Verilog, SystemVerilog, Perl, or Python and understanding... ...fully verified and high performance RTL to achieve design targets.What we...SeniorFull timeNvidia
Santa Clara, CA5 days ago$119.8k - $234.7k
..., Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’... ...infrastructure.We are looking for a Senior Performance Verification Engineer - SoC to join the team.#SCHIEResponsibilitiesEstablish... ...standard HDLs like System Verilog/UVM.Experience developing tests targeting...SeniorOngoing contractPermanent employmentWork at officeLocal areaWorldwide3 days per weekMicrosoft
Mountain View, CA3 days ago$168k - $264.5k
...seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP... ...code and functional coverage of all the RTL which you will verify.Work with and... ...GDB).Background with System Verilog and UVM based methodology for ASIC verification...SeniorFull timeNvidia
Santa Clara, CA6 days ago$200k - $300k
...Overview We are looking for a talented Senior Formal Verification Engineer to define, own, and scale the formal... ...design, working with architects, RTL, and verification teams to prove... ...SIMD units. ~ Deep expertise with SystemVerilog Assertions (SVA) and formal property...SeniorFlexible hoursVelaura AI, Inc.
Santa Clara, CA3 days ago
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Senior RTL Verification Engineer — SystemVerilog & UVM. Be the first to apply!
Related searches
- validation consultant Palo Alto, CA
- senior design verification engineer Palo Alto, CA
- verification engineer Palo Alto, CA
- computer system validation engineer Palo Alto, CA
- senior verification engineer Palo Alto, CA
- verification & validation engineer Palo Alto, CA
- validation engineer Palo Alto, CA
- validation specialist Palo Alto, CA
- senior validation engineer Palo Alto, CA
- senior living Palo Alto, CA