Senior Design Verification Engineer — Emulation, UVM & AMS (Hybrid)
Lightmatter
Lightmatter is hiring a Design Verification Engineer in Mountain View to advance verification across digital, analog, and photonic devices using UVM and emulation. You will work with digital and photonic designers to define robust validation flows and scalable test bench components to ensure high coverage. The role offers collaboration with Architecture and DV teams, exposure to post-silicon validation and AMS verification, and a hybrid work model in a cutting-edge photonics-enabled data center #J-18808-Ljbffr Lightmatter
- ...Enterprise in Sunnyvale, CA seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive... ...tape-out. You will build robust UVM testbenches, run constrained-random... ...on hardware accelerators in a hybrid work model. #J-18808-Ljbffr Hewlett...Senior
- Hewlett Packard Enterprise is seeking a Senior Design Verification Engineer to advance emulation-based verification for complex... ...define verification plans, build robust UVM/testbench environments, and drive coverage to closure in a hybrid work model with ~2 days in the...SeniorWork at office
$153.5k - $310.5k
## Senior Design Verification EngineerApplylocations: Sunnyvale, California... ...been designed as 'Hybrid' with a requirement... ...*Design Verification Engineer** with specialized... ...and experience in **emulation-based verification**... ...maintain, and enhance UVM/SystemVerilog-based testbench...SeniorWork experience placementWork at office2 days per week$293k
...Ampere is a semiconductor design company for a new era, leading the future... ...About the Role: As a Distinguished Emulation & FPGA Prototyping Verification Engineer, you will apply extensive,... ...throughout the day. #LI-GW1 #LI-Hybrid Ampere is an inclusive and equal...SeniorLocal area$158.5k - $321k
...Senior ASIC Verification EngineerThis role has been designed as 'Hybrid' with a requirement that you will work on... ...Electronic and VLSI engineers and internal and outsourced... ...using System Verilog/UVM ~ You will write... ...chip/sub-system and emulation testing – which gives...SeniorWork experience placementWork at officeLocal areaImmediate start2 days per week$163k - $236k
Lead comprehensive verification strategies and signoff for... ...code to generated RTL.Design and maintain advanced... ...validation and SystemVerilog/UVM for RTL timing and... ...and mentor junior engineers on the nuances of HLS... ...implementation, employing a hybrid strategy that includes...SeniorWorldwide$122.44k - $232.19k
...experienced pre-silicon verification engineers who are passionate... ...spanning software, RTL, and emulation platforms to validate... ...with architecture, design, and software teams,... ...of experience in UVM and constrained random... ...be eligible for our hybrid work model which allows...SeniorFull timeLocal areaImmediate startShift work$164.47k - $311.89k
...the RoleIntel is seeking a Senior Design Verification Engineer for the Silicon Chassis... ...verification methodologies including UVM, SVA, ABV, and co-... ...Formal, or similar) and emulation or FPGA-based verification... ...will be eligible for our hybrid work model which allows employees...SeniorFull timeInternshipLocal areaImmediate startShift work$250k - $300k
...ResponsibilitiesWork with architects, designers, post silicon and software engineers to ensure a high-quality... ....Develop and implement verification strategies, detailed... ...across simulation, emulation, and silicon bring-up... ...testbench, DPI and UVM.Excellent programming skills...Senior$119.8k - $234.7k
...Senior Design Verification Engineer Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE... ...pre-Si verification (simulation/emulation/FPGA-testing) and post-Si validation... ...system or system level Expertise in UVM based verification methodology...SeniorOngoing contractPermanent employmentWork at officeLocal areaWorldwide- ...Packard Enterprise invites a Senior ASIC Verification Engineer to join our dynamic team in Sunnyvale, CA on a hybrid schedule requiring ~2 days in office weekly. You will design, verify and validate VLSI blocks... ...benches in SystemVerilog/UVM, and collaborate with logic and...SeniorWork at office
$164.9k - $223.1k
ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV Company: The Boeing Company... ...and Polymorphism, and leverage UVM to create drivers, monitors, predictors... ...Experience with hardware emulators, especially Palladium Proficiency...SeniorPermanent employmentWork experience placementInterim roleRelocationVisa sponsorshipWork visaFlexible hoursShift workDay shift$163k - $236k
Work with designers, architects, and other stakeholders to come up with... ...development process.Plan the verification of multimedia design blocks... ...with architecture and design engineers to identify important... ...environments using system verilog and UVM. Identify and implement...SeniorWorldwide$129.2k - $209k
...outcomes.Job SummaryYour Career As a Design Verification engineer on the ASIC team, you will ensure that... ...platforms including simulation, emulation, formal verification, and silicon validation... ...Expertise in SystemVerilog and UVM Technical strength in the following areas...SeniorFull timeCasual workWork at office- ...in working in a challenging, fast-paced environment. As a Design Verification Engineer-AMS you will get to directly interact with one of TI's high-volume... ...Have" (Innovation & Automation)Advanced DV: Knowledge of UVM, as the top-level environments are built on these...Local areaImmediate start
$119.8k - $234.7k
...Hardware, and Infrastructure Engineering (SCHIE) is the team... ...SCHIE is responsible for design, development, manufacturing... ...infrastructure. We are looking for a Senior Silicon Design Verification Engineer to join the team... ...FPGA prototyping or emulation platforms (such as HAPS...SeniorOngoing contractPermanent employmentWork at officeLocal areaWorldwide3 days per week$168k - $264.5k
...NVIDIA is seeking best‑in‑class ASIC Verification Engineers to verify the design and implementation of the world’s... ...Universal Verification Methodology (UVM) Experience with design and... ...eligible for equity and benefits. #LI-Hybrid Applications for this job will be...Senior$200k - $300k
...Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation... ...environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies. Collaborate with...SeniorFlexible hours- ...ASIC Design Verification Engineer As an ASIC Design Verification Engineer, you will play a critical... ...netlists. Support design testing in emulation environments. Debug issues at ASIC... ...in OOP concepts, System Verilog or UVM methodology. Experience leading verification...Senior
$167.7k - $245.2k
...full product development—from design to qualification to... ...Impact As an ASIC Design Verification Engineer, you will play a critical role... ...Support design testing in emulation environments. Debug issues... ...concepts, System Verilog or UVM methodology. Experience leading...SeniorFull timeTemporary workLocal areaFlexible hours$148.5k - $165k
...at Role Overview As a Senior Design Verification Engineer, you will help define and deliver... ...~ Build and enhance reusable UVM-based SystemVerilog testbenches, agents... ...protocol checkers, formal verification, emulation, or hardware acceleration methodologies...SeniorFlexible hours$200k
...Design Verification Engineer We are looking for talented Design Verification Engineers to help verify and deliver Velaura... ...environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies. Collaborate with...SeniorFlexible hours- ...are seeking a high‑impact Design Verification Engineer with strong technical depth... ...Development Develop robust UVM‑based testbench... ...validation, firmware, and emulation/HAPS teams to ensure high‑quality... ...sponsorship. #LI-RF1 #LI-hybrid Benefits offered are...Senior
$237k - $296k
...are seeking a high-caliber Sr. Staff Design Verification Engineer to join our ADAS and Inference Silicon... ...Methodology: Leverage SystemVerilog/UVM for Coverage-Driven Verification (CDV... ...with firmware teams using Emulation and FPGA prototyping to run full-stack...SeniorFull timeContract workTemporary workPart timeLocal areaShift workNight shift$163k - $236k
Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance... ...using SystemVerilog and UVM.Identify and write all types of coverage...SeniorWorldwide- ...in Silicon Valley is seeking an experienced RTL Verification Engineer to ensure the functionality of complex digital designs for ASIC/FPGA platforms. You will build robust... ...The ideal candidate has hands-on SystemVerilog, UVM, and Python experience and will drive...Senior
$120k - $225k
...Description We’re hiring experienced Design Verification Engineers to play a key role in developing and... ...modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the... ...development and execution using UVM or other advanced DV methodologies....Senior- ...Corporation in Santa Clara, CA is seeking a Senior Verification Engineer to join our Emulation division on-site. You will verify... ...using emulation, collaborate with Design, DV, Power, and Silicon Validation... ..., VHDL, SystemVerilog, C/C++, UVM, and Python/Perl. NVIDIA offers...
- ...CPU subsystem and standard interfaces using SystemVerilog/UVM. Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional... ..., and exception handling. Execute regressions, debug RTL/design issues, and drive functional and code coverage closure....Senior
$136k - $218.5k
We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU... ...IPs using advanced verification methodologies such as UVM.Build reusable bus functional models, monitors, checkers...SeniorFull time
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