Senior Design Verification Engineer - Emulation Expert
Hitecglobal
Hewlett Packard Enterprise is seeking a Senior Design Verification Engineer to advance emulation-based verification for complex digital designs. You will define verification plans, build robust UVM/testbench environments, and drive coverage to closure in a hybrid work model with ~2 days in the office in Sunnyvale, CA. The role requires 5–8 years in design verification, SystemVerilog/UVM expertise, and hands-on emulation experience (Cadence Palladium, Synopsys ZeBu, Mentor Veloce). #J-18808-Ljbffr Hitecglobal
Vacancy posted 2 days ago
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