Senior ASIC Design Verification Engineer

ASIC Design Verification Engineer

As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You will define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms, contribute to a multi-disciplined engineering teams to meet the power, performance, and area goals for products. You will:

• Drive the definition, architecture, and design of high-performance ASICs while owning complex or multiple functional areas.
• Define new verification methodologies to support advanced design architectures and develop re-usable code for future projects.
• Lead design verification effort by solving block-level issues and participate in cluster and chip-level issue resolution, and drive reviews to recognize areas of architectural concerns.
• Architect, develop, and maintain cluster and top-level Design Verification (DV) environment infrastructure.
• Build DV environments from scratch for cluster and chip levels.
• Develop, implement, and enhance test plans and tests for cluster and chip verification, using both constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations with timing annotation on netlists.
• Support design testing in emulation environments.
• Debug issues at ASIC, SW and Systems levels and help in lab bring-up and post silicon validation.

Minimum Qualifications:

• Bachelors degree in Computer, Electrical or Electronics Engineering, + 7 years of relevant technical experience, or Masters degree + 4 years of relevant technical experience with a focus on ASIC design and verification.
• Experience in OOP concepts, System Verilog or UVM methodology.
• Experience leading verification teams or assignments projects.
• Experience with scripting using Perl and/or Python.

Preferred Qualifications:

• Experience with forwarding logic, parsers, or P4.
• Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Knowledge of formal verification tools (e.g., IEV or VC Formal).
• Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.