Physical Design Engineer

Sunnyvale, CA, USA Required Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience. 4 years of experience with physical design from RTL to GDSII, including synthesis, floor planning, place and route, and timing closure. Experience with scripting languages in one or more of the following: Perl, Python, or Tcl. Preferred Qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in floor planning, block integration, static timing analysis, sign-off. Experience executing low‑power physical design implementation using industry‑standard EDA tools (Innovus/FC). Experience in sign‑off convergence including STA, electrical checks, and physical verification. Experience utilizing AI techniques for faster and optimal Physical Design Convergence (e.g., timing, floorplanning, power grid, and clock tree design). About the Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate closely with cross‑functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro‑architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power, and Area (PPA) for the next generation of TPU blocks and sub‑chips. Responsibilities Perform physical design of complex blocks from Register-Transfer Level (RTL) to Graphic Data System (GDS). Use problem‑solving, debugging skills and collaborate cross‑functional teams to achieve the best Power/Performance Analysis (PPA). Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized implementation and sign‑off domains. Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade‑offs for physical design closure. Compensation US: $138,000 - $198,000 (USD) + 15% bonus target + bonus + equity + benefits Equal Opportunity Employer Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. #J-18808-Ljbffr Google Inc.