Senior ASIC Design Verification Engineer

We are looking for a Senior ASIC Design Verification Engineer to contribute to the verification of complex digital and mixed-signal ASIC, SoC, subsystem, IP, and FPGA designs. This role is ideal for an experienced verification engineer who enjoys building robust verification environments, developing high-quality tests and coverage models, debugging complex issues, and collaborating closely with cross-functional engineering teams.

Job Summary
As a Senior ASIC Design Verification Engineer, you will be responsible for developing and executing verification plans for complex ASIC, SoC, subsystem, IP, and FPGA designs. You will work with architects, RTL designers, analog/mixed-signal engineers, firmware developers, and other verification engineers to ensure designs meet functional, performance, and quality requirements.

This is a hands-on technical role focused on verification environment development, test creation, coverage-driven verification, regression debug, and verification closure. You will contribute to reusable verification infrastructure and help improve verification efficiency across projects.

Key Responsibilities
• Develop and execute verification plans for ASIC, SoC, subsystem, IP, and FPGA designs.
• Build and maintain verification environments using SystemVerilog, UVM, constrained-random testing, directed testing, and assertion-based verification.
• Create and enhance testbench components, including agents, monitors, drivers, scoreboards, sequences, checkers, and coverage models.
• Develop directed and constrained-random test cases to verify functional requirements and corner cases.
• Analyze design specifications and collaborate with architects and RTL designers to identify verification requirements.
• Drive verification closure using functional coverage, code coverage, assertion coverage, regression results, and bug tracking.
• Debug RTL, testbench, and integration issues using simulation logs, waveforms, coverage data, and EDA debug tools.
• Participate in design and verification reviews, providing technical feedback on specifications, test plans, coverage models, and verification results.
• Support regression development, automation, and continuous improvement of verification flows.
• Work closely with design, firmware, analog/mixed-signal, FPGA, and program teams to resolve issues and achieve project milestones.
• Contribute to verification methodology improvements, reusable verification components, and project-level best practices.
• Mentor junior engineers as appropriate through code reviews, debug support, and technical guidance.

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Required Skills & Experience

Qualifications
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Typically 5+ years of ASIC, SoC, FPGA, or IP design verification experience.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience developing block-level, IP-level, subsystem-level, or SoC-level verification environments.
• Experience creating verification plans, test cases, sequences, scoreboards, checkers, assertions, and functional coverage models.
• Solid understanding of constrained-random verification, directed testing, regression management, and coverage-driven verification closure.
• Strong debug skills for RTL, testbench, and integration issues.
• Experience with scripting and automation using languages such as Python, Perl, Tcl, shell scripting, or Make.
• Familiarity with industry-standard EDA tools for simulation, waveform debug, coverage analysis, or verification management.
• Ability to read and interpret design specifications, microarchitecture documents, and protocol documentation.
• Strong problem-solving skills and attention to detail.
• Effective written and verbal communication skills.
• Ability to collaborate effectively with architecture, design, verification, analog, firmware, FPGA, and program teams.


Nice to Have Skills & Experience

Preferred Qualifications
• Experience verifying complex SoCs, processors, accelerators, networking devices, high-performance datapaths, or AI/ML-oriented designs.
• Experience with high-speed interfaces and protocols such as PCIe, CXL, DDR, LPDDR, Ethernet, USB, MIPI, AMBA, AXI, CHI, or UCIe.
• Experience with formal verification, assertion-based verification, or property checking.
• Experience with gate-level simulation, low-power verification, UPF/CPF, reset verification, or X-propagation analysis.
• Experience with emulation, FPGA prototyping, hardware/software co-verification, or post-silicon bring-up support.
• Familiarity with mixed-signal verification methodologies.
• Experience working in customer-facing engineering environments or ASIC design services organizations.
• Experience mentoring junior engineers or contributing to project-level methodology improvements.


Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.