ASIC/SoC Design & Verification Engineer

About the Role

This role is for one of our clients.

Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.

Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.

This is a fully remote, part-time engagement requiring approximately 20–40 hours per week, depending on your availability.

Key Responsibilities

• Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
• Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
• Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
• Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
• Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
• Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.

Requirements

• Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
• Strong proficiency in SystemVerilog and Verilog.
• Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
• Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
• Deep expertise in one or more of the following areas:
• RTL Design and Microarchitecture
• Functional Verification (UVM, SVA, Cocotb, testbench development)
• IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
• Formal Verification and Coverage Closure
• Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
• Analog/Mixed-Signal Design Verification
• Hardware Specification Development and Technical Documentation
• Ability to commit 20–40 hours per week with reliable weekday availability.
• Strong written communication skills and the ability to work independently in a remote environment.

Preferred Qualifications

• Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
• Graduate research or industry experience in semiconductor design, verification, or computer architecture.
• Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
• Experience mentoring engineers or reviewing complex technical designs.