Senior RTL Design Engineer - AI/SoC, Equity
$160k - $220kDelos Data
Delos Data is looking for an experienced Senior RTL Design Engineer in Palo Alto, California, to design and implement high-quality RTL for complex digital systems. The role involves translating architectural specifications and collaborating with cross-functional teams. The ideal candidate has over 5 years of RTL design experience and strong proficiency in Verilog/SystemVerilog. The target salary ranges from $160,000 to $220,000 per year, along with equity and benefits. #J-18808-Ljbffr Delos Data
Vacancy posted 4 days ago
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