Senior RTL Design Engineer - Edge AI & Low-Power SoC
present of AI
Efficient Computer in San Francisco (also listed for Bay Area, Pittsburgh, PA and Austin, TX) seeks a senior RTL design engineer to own block level design, integration and sign-off for complex SoC components. You should bring strong Verilog or SystemVerilog, timing closure and low‑power techniques, plus familiarity with on‑chip interconnect and memory interfaces. Work focuses on hardware that runs AI models with very low power for edge devices. #J-18808-Ljbffr present of AI
Vacancy posted 2 days ago
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