Senior CPU Gate-Level Synthesis Engineer

Apple's Silicon Engineering Group (SEG) is seeking a CPU Gate Level Synthesis Engineer to drive early-stage development of high-performance, low-power CPUs. You will run RTL to gate-level synthesis and seek opportunities to optimize timing, power, and area while collaborating across RTL, physical design and DFT teams. The role requires a BS and 10+ years in digital logic, RTL synthesis and physical design, with preferred CPU implementation experience and scripting skills in Tcl, Perl or Python. #J-18808-Ljbffr