Senior DFT Methodology Engineer
$168k - $264.5kNvidia
We are now looking for a Senior DFT Methodology Engineer! As a Senior DFT Methodology Engineer, you will architect and develop the test methodologies that make our next generation of silicon testable, debuggable, and secure from the very first bring-up. NVIDIA has crafted creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry’s most complex semiconductor chips. This powerful technology changed modern computer graphics and parallel computing.NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.What you'll be doing:As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump and DFX security methodology.You will partner closely with timing, physical design, software, bring-up, and production teams to make the right trade-offs between cost and quality.In addition, you will help architect, develop and deploy DFT methodologies for our next generation products including RTL design, Verification, pattern generation, partnering with teams like timing, physical design, software, bringup, productionYou will also help mentor junior engineers on test designs and trade-offs including cost and quality.What we need to see:BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience10+ years of hands-on experience in SoC architecture, RTL design, and verification.Strong analytical skills, with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs.Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offsExperience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program developmentExceptional written and oral interpersonal skills with the curiosity to work on rare challengesWays to Stand out from the Crowd:Knowledge of DFT security and hardware system security is a plus.Strong programming and scripting skills in Perl, Python, or TclProven track record of successfully deploying advanced DFT methodologies in groundbreaking semiconductor technologiesExperience mentoring engineers and driving methodology adoption across multiple product generationsStrong problem-solving skills and a proactive approach to overcoming technical challengesWhy Join Us? This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until October 6, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time
- ...NVIDIA seeks a Senior DFT Methodology Engineer to architect and develop test methodologies for next-generation silicon, ensuring testability, debugability, and security from bring-up. You will collaborate across RTL, timing, physical design, software, and production to...Senior
$168k - $264.5k
...choice to join us today.Design-for-X Engineering at NVIDIA works on groundbreaking innovations... ...chips.What you'll be doing:As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas.This will include working on...SeniorFull time- Job description Senior DFT EngineerMoTek Technologies has an immediate opening for a Senior DFT Engineer:The ideal candiate will be responsible for DFT flows and implementation... ...fault isolation of pattern failures ATPG methodology, Silicon bringup, and process yield...SeniorImmediate start
$168k - $264.5k
As a Senior DFT Engineer - Post-Silicon , you will take pioneering DFT capabilities beyond implementation—connecting silicon behavior, test... ...with clear metrics/what-if analysis.Define and improve methodologies for silicon bring-up, failure analysis, test-content validation...SeniorFull time$196k - $310.5k
...Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated...Senior$136k - $218.5k
...choice to join us today.Design-for-Test Engineering at NVIDIA works on groundbreaking innovations... ...crafting creative solutions for DFT architecture, verification and post-silicon... ...addition, you will help develop and deploy DFT methodologies for our next generation products. You...SeniorFull time- ...Job Description: ~5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs ~ Strong understanding of DFT fundamentals... ...test architectures and diagnostics ~ Knowledge of IO Test methodologies for interface and pin level validation ~ Solid understanding...Senior
$167.7k - $245.2k
...to verify comprehensive Design-for-Test (DFT) architecture that supports ATE... ...diagnostics needs of the designOwn the MBIST methodology across the Silicon One portfolio, driving... ...QualificationsBachelor’s in Electrical Engineering or equivalent with at least 7+ years (or...SeniorFull timeTemporary workLocal areaFlexible hours3 days per week$167.7k - $245.2k
...to verify comprehensive Design-for-Test (DFT) architecture that supports ATE... ...stacked die, driving re-usable test and debug methodologies and standards. The job requires the candidate... ...Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or...SeniorFull timeTemporary workLocal areaFlexible hours3 days per week$167.7k - $245.2k
...to verify comprehensive Design-for-Test (DFT) architecture that supports ATE... ...stacked die, driving re-usable test and debug methodologies and standards. The job requires the candidate... ...Bachelor's in Electrical Engineering or equivalent with at least 7+ years (or...SeniorFull timeTemporary workLocal areaFlexible hours3 days per week$168k - $264.5k
...on the world.We want a skilled and motivated Implementation Methodology Engineer for NVIDIA's elite VLSI team. This role involves owning synthesis... ...-assisted flow optimization.Partner with architecture, RTL, DFT, physical build, and sign-off teams to surface PPA...SeniorFull time- ...Cisco's Silicon One team in San Jose seeks an experienced engineer to lead test planning and DFT verification for next‑gen silicon. You will develop test benches and own MBIST methodology across the portfolio, collaborating with RTL and physical design teams to ensure...Senior
$168k - $264.5k
...the world.Join NVIDIA's Design-for-Test Engineering team in Santa Clara, CA, where we are... ...to solve emerging challenges. As a Senior DFT - Silicon Validation Engineer, you will... ...drive the end to end DFT architecture and methodologies to accelerate the post silicon bring...SeniorFull timeShift work- ...Cisco Systems, Inc. is seeking a senior engineer for the Silicon One development organization to push high-quality DFT RTL and robust silicon solutions, collaborating with front-end RTL and backend physical design teams to align with Cisco's scalable architecture. The...Senior
$168k - $264.5k
...best work. Come join the team and see how you can make a lasting impact on the world.We are seeking an innovative Senior STA Signoff Methodology Engineer to help drive sign-off strategies for the world's leading GPUs, CPUs, LPUs and SoCs. This position is a broad opportunity...SeniorFull time- ...Etched is seeking a highly skilled Design For Testability (DFT) Engineer to ensure robust testability of ICs from design to production. You will develop DFT architectures, integrate scan, boundary scan, BIST, MBIST, and work with design/verification teams to improve coverage...Senior
$168k - $264.5k
...teams with the smartest people in the world. Join us at the forefront of technological advancement.We are looking for a Senior Circuit Methodology Engineer that will work closely with Nvidia's circuit design engineering team in the area of infrastructure support as it...SeniorPermanent employmentFull timeWork experience placement- ...Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in the Silicon One development organization. You will be a detail-oriented engineer with strong timing expertise, collaborating with cross-functional teams to manage clocks, constraints, and DFT flows. The role...Senior
$136k - $218.5k
...the world.Are you excited to build the automation infrastructure behind next-generation silicon design? We’re seeking a Senior VLSI Methodology Engineer to join our team and to design automation that powers library modeling, quality checks, and release for NVIDIA’s PD...SeniorFull time- ...Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer to join the Silicon One development organization in San Jose. You will drive timing constraints, DFT/STA strategies, and work across RTL design, CDC/RDC, and verification efforts to enable successful post-silicon...Senior
- ...Cisco Systems, Inc. in San Jose, CA, is seeking a senior RTL design engineer focused on Design for Test (DFT) for Silicon One. You will collaborate with front-end RTL and backend physical design teams to deliver robust silicon solutions and ensure performance and reliability...Senior
$135k - $160k
...the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our... ...and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck‑at, transition, and...SeniorPermanent employmentTemporary workWorldwideWeekend work- ...NVIDIA is seeking a Senior VLSI Methodology Engineer in Santa Clara, CA to design automation for library modeling, validation, and release of PD flows. You will build scalable validation pipelines, integrate data-driven dashboards, and collaborate with design teams to...Senior
- ...Etched.ai, Inc. is seeking a Design For Testability (DFT) Engineer to enhance the testability of integrated circuits. The ideal candidate will develop DFT architectures, collaborate on design requirements, and ensure robust test strategies during production. This position...SeniorRelocation package
$168k - $264.5k
...turn power and thermal design into executable productization methodology. Power and thermal are among the most complicated problems we... ...role, you will help us build that bridge. We're looking for an engineer who reasons from first principles, flourishes with ownership in...SeniorFull time$168k - $264.5k
We are now looking for a Senior Circuit Timing Engineer!NVIDIA stands at the intersection of hardware excellence... ...analysis.Develop timing models and methodology for innovative and unique custom... ...constraints, timing and power convergence, DFT, as well as timing ECO implementation...SeniorFull timeWorldwideShift work$163k - $236k
...qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science,... ...ASICs. You will develop static timing methodologies, margins, automation scripts, and write... ...with architecture, logic design, and DFT teams to understand and implement their...SeniorFull timeWorldwide$144k - $230k
...world.We are seeking a highly skilled Senior Failure Analysis (FA) Engineer to drive die-level logic fault... ...closely with our Design, Test, and DFT teams to identify root causes of silicon... ...and electrical fault isolation methodologies.ATE Testing & Debugging: Utilize the...SeniorFull time$185k - $240k
...Principal / Senior Principal Electrical Design Engineer San Jose, California, United States Astera Labs (... ...board architecture, establish design methodologies, drive innovation in high-speed... ...-excellence initiatives including DFT, DFM, and DFR to systematically improve...SeniorContract workFlexible hours$168k - $258.75k
NVIDIA is seeking a highly skilled Senior PCB Library Engineer to own the development, validation, and... ...design quality.Apply strong DFM, DFA, and DFT principles to all library... ...development procedures, and quality control methodologies.Support advanced technologies including...SeniorFull time
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