Principal SoC Solutions Engineer-18804

You Are:

You are an experienced SoC design, verification, or implementation engineer with deep expertise in Memory Interface and Interface IP. You combine hands-on experience developing subsystem and/or SOC level designs, integrating complex IP subsystems into SoCs, validating full-system functionality, and supporting silicon bring-up. You have a proven track record of transforming advanced IP technologies into production-ready solutions and thrive on solving complex technical challenges while helping Synopsys customers successfully adopt industry-leading technologies.

You are passionate about working at the forefront of semiconductor innovation and enjoy collaborating with industry leaders to enable next-generation computing, AI, networking, automotive, and mobile platforms.

What You'll Be Doing:

• Leading technical customer engagements for the integration, bring-up, and deployment of Memory Interface PHY and Controller IP, including HBM, DDR, and LPDDR solutions.
• Developing reference designs and subsystem-level architectures that demonstrate best practices for integrating Synopsys IP into complex SoC environments. Driving subsystem verification, validation, and silicon readiness to accelerate customer adoption and deployment.
• Applying hands-on expertise to integrate memory and interface IP into production SoC designs, with demonstrated success bringing subsystems from architecture and verification through silicon bring-up and production.
• Solving complex customer challenges involving IP integration, performance optimization, interoperability, silicon bring-up, and deployment across advanced design environments.
• Serving as a key technical interface between customers and internal engineering teams to demonstrate integration methodologies, resolve technical issues, reduce deployment risk, and accelerate time-to-market.
• Providing technical leadership, training, workshops, and presentations to support customer implementation, architecture decisions, and technology adoption.
• Bringing customer feedback and deployment insights back to product and engineering teams to improve product quality, usability, integration flows, and deployment readiness.
• Staying at the forefront of evolving industry technologies and architectures, including DDR5, LPDDR6, MRDIMM2, HBM4, PCIe, Ethernet, CXL, and UCIe, while helping shape how these technologies are adopted in next-generation SoC platforms.

The Impact You Will Have:

• Accelerate successful adoption and deployment of Synopsys Memory Interface and Interface IP by demonstrating proven integration methodologies, validated reference designs, and production-ready subsystem solutions.
• Enable customer success through deep technical expertise and hands-on experience integrating PHYs, Controllers, VIP, and memory components into complex SoC architectures.
• Help customers reduce design risk and improve time-to-market through validated integration flows, silicon-proven solutions, and technical leadership.
• Influence future product enhancements by connecting real-world customer requirements and deployment challenges with internal engineering and product teams.

• Drive adoption of next-generation interface technologies and contribute to industry-leading SoC architectures that power AI, hyperscale computing, networking, automotive, and mobile applications.
• Reinforce Synopsys' leadership in advanced interface IP through technical excellence, innovation, and trusted customer partnerships.

What You'll Need:

• Bachelor's or Master's degree in Electrical Engineering , Computer Engineering, or a related field, ideally with a VLSI focus.
• 15+ years of industry experience in SoC design, verification, implementation, or silicon development. Hands-on experience with Memory Interface IP such as DDR, LPDDR, and HBM, or Interface IP such as PCIe, Ethernet, CXL, or UCIe.
• Proven experience developing reference designs, integrating complex IP subsystems into SoCs, and successfully delivering silicon-proven solutions into production.
• Hands-on experience with subsystem architecture, verification, silicon bring-up, system validation, and post-silicon problem-solving.
• Strong understanding of Controller IP, PHY integration, AMBA/AXI interfaces, ASIC design flows, SoC architecture, and backend design considerations.
• Proficiency with Linux, Verilog/ SystemVerilog , simulation and debug environments, and modern ASIC development methodologies.
• Excellent communication and collaboration skills, with the ability to work effectively across customer, R&D, product, and engineering organizations.

Who You Are:

• A hands-on technical leader who can independently architect, integrate, verify, and troubleshoot complex SoC subsystems.
• A successful track record of bringing advanced IP solutions from concept and integration through silicon validation and production deployment.
• A strong collaborator who can effectively bridge customer needs with product, architecture, and engineering teams.
• An effective communicator capable of translating complex technical concepts into clear implementation guidance and best practices.
• A continuous learner who is energized by emerging technologies and enjoys working on architectures that shape the future of the semiconductor industry.

The Team You'll Be A Part Of:

You will join a global team within the Interface IP Group focused on SoC Solutions and Customer Success across Memory Interface and Interface IP technologies . The team develops reference architectures, validates subsystem solutions, and works closely with leading semiconductor companies to enable successful deployment of next-generation IP technologies.

This role offers a unique opportunity to work directly with industry-leading SoC architects and engineering teams, gain exposure to cutting-edge semiconductor technologies, and play a key role in the success of emerging industry trends spanning AI, high-performance computing, networking, automotive, and mobile markets.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Details will be provided during the hiring process.

#LI-DP1