Senior Memory Validation Engineer

Job Description

Job Description

Senior Memory Validation Engineer

Location: Santa Clara, CA | Candidates must currently reside in California
Schedule: Full-Time M-F, 4 days onsite
Compensation: $152,000 - $179,000 base salary. Base salary is determined based on location, experience, and the pay of employees in similar positions. Compensation package also includes new-hire RSU grants, the opportunity for annual RSU grants, and highly competitive benefits.

About the Company

Our client is a leading fabless semiconductor company at the forefront of edge AI-based computer vision. Their SoCs (Systems-on-Chips) power applications ranging from autonomous driving and ADAS to intelligent video security and robotics.

They are building the next generation of Edge AI, operating at the intersection of high-performance hardware and real-world software deployment.

The Opportunity

Memory is where a lot of system-level problems come to die. Marginal timing, a corner-case power state transition, or a customer platform that fails one boot in ten thousand—these issues are expensive to reproduce, slow to root-cause, and they tend to come back.

We’re looking for an engineer to join the ASIC design team and help change that. You’ll own the data and automation layer for the memory subsystem: building test infrastructure that catches instability early, turning lab and field data into insight, and feeding what you learn back into the design of next-generation memory controllers.

This is a hands-on role combining silicon bring-up, hardware debugging, and automation, with real visibility across architecture, field, and validation teams. The work you do will help shape both current products and future memory controller designs.

Responsibilities

• Own the memory training and calibration code. Develop, maintain, and tune the training and calibration routines that get LPDDR5/5X and LPDDR6 running reliably at speed across parts, boards, and operating conditions.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis—expanding test coverage while cutting cycle time.
• Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
• Turn system behavior and failure analysis into insights that measurably improve memory controller robustness and performance.
• Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
• Validate power-saving features, characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

Required Qualifications

• 4+ years of experience in memory validation, memory controller design, SoC validation, or a closely related area.
• Hands-on experience with LPDDR5/5X and LPDDR6 and working familiarity with relevant JEDEC specifications.
• Experience owning or contributing to memory training and calibration code, with the C/firmware skills to maintain it.
• Strong Python (or equivalent) skills for test automation and data analysis.
• Practical debugging skills on real hardware, including bench instrumentation, protocol analyzers, logic analyzers, and boot and stability failure triage.
• Ability to analyze large volumes of shmoo, margining, or regression results and identify meaningful patterns and issues.
• Ability to work directly with customers and cross-functional teams under time pressure.

Preferred Qualifications

• Silicon bring-up or post-silicon validation experience on a production program.
• Understanding of signal integrity fundamentals, including eye diagrams, jitter, and timing margin analysis on high-speed interfaces.
• Experience with low-power state validation, including self-refresh, power-down, and DVFS-style transitions.
• Statistical analysis, machine learning, or dashboarding experience applied to hardware validation data.
• Firmware or driver-level exposure to the memory stack.