Software Engineer — RISC-V Random Test Generator

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > CPU EngineeringGeneral Summary:About the Role You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA — including privileged modes, virtual memory, interrupts, vector, and cryptography extensions. The assembler library provides the bit-accurate instruction encoding layer that the RTG and other tools consume. What You'll Do Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences. Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers). What We're Looking For 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.Solid Python 3 skills; comfort with generator-based coroutines and object- oriented design patterns. Working knowledge of the RISC-V ISA: instruction encoding formats ( R/I/S/B/ U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model. Alternatively, similar knowledge for x86 or ARM.Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.Exposure to random test generation flows or ISS/RTL co-simulation is a plus. Nice to Have Compiler development experience.Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.Familiarity with constraint-propagation libraries.Minimum Qualifications:• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.ORMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.ORPhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.Qualcomm is an equal opportunity employer. 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Qualcomm is not responsible for any fees related to unsolicited resumes/applications.EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.Pay range and Other Compensation & Benefits :$175,600.00 - $263,400.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. 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