Senior Analog Design Lead, High-Speed LPDDR PHYs
AMD
AMD is looking for a candidate to manage its Memory I/O design team in Boxborough, MA. This role will focus on defining and designing LPDDR IPs, working with critical analog and digital blocks. You will ensure optimal implementation of the PHY architecture through close collaboration with various disciplines, lead execution across stakeholders, and contribute to design and documentation processes. Ideal candidates will have extensive experience leading multiple IPs and knowledge of high-speed design techniques. #J-18808-Ljbffr AMD
Vacancy posted 1 day ago
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