Principal R&D Engineer, 18023

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent your career at the leading edge of physical design, where every nanometer matters and “good enough” is never the answer. You see the connections between advanced node process changes, DTCO knobs, and the real-world tradeoffs that drive Power, Performance, Area, and Runtime. You do not just run flows; you dissect them, spot the bottlenecks before they become showstoppers, and know how to make a tool bend to the needs of a bleeding-edge designs sometimes with a fast TCL prototype, sometimes by guiding the core engine itself. You thrive on ambiguity, especially when it means working with foundry partners and internal R&D to define what “possible” looks like next year. You are happiest when you can move from the whiteboard to the code, then see your work land in a tape out that sets a new bar for industry. You never lose sight of the bigger picture, always asking: “How do we close PPA faster and smarter for the next node?” If you want to be at the intersection of technology, methodology, and impact, you will feel at home here. What You'll Be Doing Partnering with Advanced Node Methodology and R&D teams to deliver rapid PPA closure on high-performance designs using Fusion Compiler Connecting design requirements, DTCO optimization, and EDA engine capabilities to drive measurable improvements in Power, Performance, Area, and Runtime Prototyping quick solutions using TCL and Perl to validate and extend EDA engine functionality in response to customer and internal challenges Collaborating directly with foundry partners to influence technical strategy and execution for advanced node enablement (2nm, 1.4nm, and beyond) Analyzing and enhancing RTL2GDS flows, identifying critical path issues, and proposing tangible algorithms or methodology changes Leading benchmarking and tape out efforts to validate new methodologies on real, high-performance core designs Providing deep technical guidance to both internal teams and external customers on advanced node physical design, including Backside Routing and Std Cell Library analysis The Impact You Will Have Accelerate PPA closure for next-generation designs, making Synopsys tools the clear choice for high-performance customers Shape the direction of EDA engine development by surfacing real-world challenges and demonstrating actionable solutions Shorten turnaround times from design concept to tape out, directly impacting customer time-to-market Influence foundry technical roadmaps by bringing grounded, design-driven insights to process and tool co-optimization Raise the bar for quality of results (QoR) in advanced node flows, ensuring that every new release delivers measurable value Enable the deployment of new physical design methodologies that scale across multiple customers and use cases Mentor and elevate your peers by sharing best practices, code snippets, and lessons learned from the front lines What You'll Need BS or MS in Electrical Engineering, Computer Engineering, or a closely related field with 12+ years of hands‑on EDA product development, deployment, and full‑flow benchmarking experience, including design tape outs at advanced nodes Deep expertise in RTL2GDS flows, including Synthesis, Place & Route, and physical verification for high-performance cores Strong scripting skills with TCL and Perl, with a track record of building practical prototypes and workflow extensions Demonstrated experience with advanced node technologies (2nm, 1.4nm and below), including Backside Routing and Std Cell Library analysis Solid understanding of how Synthesis and Place & Route engines interact to deliver and optimize QoR Experience with Synthesis/Optimization cell selection is a plus Who You Are You can spot a PPA bottleneck by reading a timing report You are comfortable jumping between customer conversations, foundry meetings, and hands‑on code fixes You explain why a DTCO tradeoff matters in terms that both designers and tool developers understand You thrive on ambiguity and treat new process nodes as an invitation, not a roadblock You act fast, prototype early, and bring concrete evidence to technical arguments You mentor others—sharing scripts, lessons, and war stories to raise the team’s technical game The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr Synopsys Inc