Senior FPGA Engineer

Job Description We are seeking a dynamic and experienced Senior FPGA Engineer to design and develop advanced FPGA and SoC systems used in high performance communications products, working through the full lifecycle from architecture to implementation, simulation, and hardware testing. This role focuses on creating and integrating complex IP using VHDL or System Verilog, optimizing high speed data paths, developing C and C++ drivers, and collaborating with hardware, software, and systems teams to build reliable, high throughput digital communication solutions. The ideal candidate has deep experience with FPGA toolchains such as Xilinx Vivado or Intel Quartus, strong knowledge of AXI based SoC designs, expertise in timing closure and simulation workflows, and hands‑on experience with gigabit transceiver protocols and modern networking standards. Additional Responsibilities Design, develop, document, debug and test FPGA SoC systems; including IP integration into FPGA, projects (synthesis/implementation), high‑performance FPGA IP (VHDL/SystemVerilog), user‑space drivers for FPGA, IP (C++), firmware for embedded microcontrollers. Utilize strong communication skills to effectively work and communicate with team members and engineering management. Skills and Requirements Bachelor's in electrical or computer engineering (or related degree). 5+ years of experience in FPGA/ASIC SoC design. Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired). Working knowledge of embedded Linux: kernel / Yocto / U‑Boot / DeviceTree. Working knowledge with SATCOM waveforms like DVB‑S2X and/or 5G NTN 3GPP Rel 17/18. Working knowledge of communication networks and security within a zero‑trust environment. Experience with Partial Reconfiguration/DFX or PCIe CvP. Possess an active DoD clearance or demonstrate readiness to obtain one - strong digital design engineer with FPGA/ASIC SoC design experience. Strong FPGA implementation with Altera Quartus or Xilinx Vivado. Experience designing/debugging SoC systems with AMBA‑compliant AXI and APB interfaces. Experience designing fmax‑optimized, high‑throughput, pipelined AXI‑Stream IP. Capable of creating RTL simulations to identify and resolve most issues before hardware tests. Knowledgeable in static timing analysis (STA) and Synopsis design constraints (SDC). Experience analyzing STA reports and post‑synth netlist/placement to resolve failing paths. Experience contributing to schematic capture and layout for FPGA portions of PCB designs. Experience implementing at least one gigabit transceiver protocol such as PCI Express, Interlaken, USB SuperSpeed.

1000BASE‑X/SGMII, 10GBASE‑R, 40GBASE‑4, 100GBASE‑R4

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